17 lines
309 B
Verilog
17 lines
309 B
Verilog
// Check that it is an error if the number of unpacked dimensions do not match
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// in an continuous array assignment, even if the canonical size of the array is
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// the same.
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module test;
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wire [1:0] x[1:0][1:0];
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reg [1:0] y[3:0];
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assign x = y;
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initial begin
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$display("FAILED");
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end
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endmodule
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