iverilog/tgt-vvp
Cary R df177e9e14 Major rewrite of indexed part selects.
This patch is a major rewrite of the indexed part selects (+: and -:).

It made the following enhancements:

1. Make indexed part selects work correctly with both big and little
   endian vectors.

2. Add a warning flag that warns about constant out of bounds/or 'bx
   indexed selects.

3. Moved the -: parameter code to its own routine.

4. Added support for straddling before part selects in a CA.

5. Added more assert(! number_is_unknown) statements.

6. Add warning for &PV<> select with a signed index signal that is
  less than the width of an int. This will be fixed later.

7. Add support for loading a 'bx/'bz constant into a numeric register.

8. Add a number of signed value fixes to the compiler/code generator.

9. Major fix of draw_select_expr() in the code generator.
(cherry picked from commit 2b17366ad5)
2009-09-03 18:07:51 -07:00
..
Makefile.in Update mkinstalldirs to handle paths with spaces. 2009-02-04 08:44:22 -08:00
README.txt tgt-vvp generates code that skips nets as inputs. 2001-08-10 00:40:45 +00:00
draw_mux.c Assert number is not unknown for many cases in tgt-vvp. 2009-09-03 18:01:43 -07:00
draw_net_input.c Assert number is not unknown for many cases in tgt-vvp. 2009-09-03 18:01:43 -07:00
draw_switch.c Content-free portability fixes. 2008-09-29 18:06:47 -07:00
draw_ufunc.c Content-free portability fixes. 2008-09-29 18:06:47 -07:00
draw_vpi.c Major rewrite of indexed part selects. 2009-09-03 18:07:51 -07:00
eval_bool.c Add support for 64 bit delays in procedural non-blocking assignments. 2009-02-17 10:32:11 -08:00
eval_expr.c Major rewrite of indexed part selects. 2009-09-03 18:07:51 -07:00
eval_real.c For real expressions evaluate non-real sub-exprs as bits and convert. 2009-06-23 09:37:41 -07:00
modpath.c Content-free portability fixes. 2008-09-29 18:06:47 -07:00
vector.c Remove most of the lingering CVS droppings. 2008-12-05 21:48:28 -08:00
vvp-s.conf.in Remove redundant back-end selections. 2008-09-07 16:43:54 -07:00
vvp.c Some compiler cleanup and minor memory leak fixes. 2009-06-23 09:14:03 -07:00
vvp.conf.in Remove redundant back-end selections. 2008-09-07 16:43:54 -07:00
vvp_config.h.in Remove most of the lingering CVS droppings. 2008-12-05 21:48:28 -08:00
vvp_priv.h Some compiler cleanup and minor memory leak fixes. 2009-06-23 09:14:03 -07:00
vvp_process.c Assert number is not unknown for many cases in tgt-vvp. 2009-09-03 18:01:43 -07:00
vvp_scope.c Major rewrite of indexed part selects. 2009-09-03 18:07:51 -07:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.


GENERAL FUNCTOR WEB STRUCTURE

The net of gates, signals and resolvers is formed from the input
design. The basic structure is wrapped around the nexus, which is
represented by the ivl_nexus_t.

Each nexus represents a resolved value. The input of the nexus is fed
by a single driver. If the nexus in the design has multiple drivers,
the drivers are first fed into a resolver (or a tree of resolvers) to
form a single output that is the nexus.

The nexus, then, feeds its output to the inputs of other gates, or to
the .net objects in the design.