iverilog/vvp/examples/time.vvp

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:vpi_module "system";
; Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
;
; This source code is free software; you can redistribute it
; and/or modify it in source code form under the terms of the GNU
; General Public License as published by the Free Software
; Foundation; either version 2 of the License, or (at your option)
; any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
; This example is similar to the code that the following Verilog program
; would make:
;
; module main;
; initial #45 $display("Hello, Clock: ", $time);
; endmodule
;
; This tests that the special $time symbol references the vpiHandle for
; the system time.
main .scope module, "main";
code
%delay 45, 0;
%vpi_call 0 0 "$display", "Hello, Clock: ", $time;
%end;
.thread code;
:file_names 2;
"N/A";
"<interactive>";