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Martin Whitaker
61c82d2cb0
SystemVerilog allows a mixture of procedural and continuous assignments to be applied to different parts of the same vector. The previous attempt to make this work for non-blocking assignments was flawed (see preceding fix for vvp_fun_part_pv::recv_vec4_pv). Instead, handle this case by converting the non-blocking assignment into a delayed force statement, which matches the way mixed continuous and blocking assignments are handled.
THE VVP TARGET SYMBOL NAME CONVENTIONS There are some naming conventions that the vvp target uses for generating symbol names. * wires and regs Nets and variables are named V_<full-name> where <full-name> is the full hierarchical name of the signal. * Logic devices Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In this case the symbol is attached to a functor that is the output of the logic device. GENERAL FUNCTOR WEB STRUCTURE The net of gates, signals and resolvers is formed from the input design. The basic structure is wrapped around the nexus, which is represented by the ivl_nexus_t. Each nexus represents a resolved value. The input of the nexus is fed by a single driver. If the nexus in the design has multiple drivers, the drivers are first fed into a resolver (or a tree of resolvers) to form a single output that is the nexus. The nexus, then, feeds its output to the inputs of other gates, or to the .net objects in the design.