14 lines
379 B
Verilog
14 lines
379 B
Verilog
// Generate frame with WHOLE-signal port connections (isolates frame
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// transparency from bit-select handling).
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module inv8 (input wire [7:0] d, output wire [7:0] q);
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assign q = ~d;
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endmodule
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module wrap (input wire [7:0] din, output wire [7:0] dout);
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generate
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if (1) begin : blk
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inv8 u_inv (.d(din), .q(dout));
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end
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endgenerate
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endmodule
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