29 lines
617 B
Verilog
29 lines
617 B
Verilog
// Phase 3 test: for-generate replicating a sub-module, plus an
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// if-generate, to exercise generate-frame emission.
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module inv #(parameter ID = 0) (
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input wire d,
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output wire q
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);
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assign q = ~d;
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endmodule
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module gen_top #(parameter N = 3) (
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input wire [2:0] din,
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output wire [2:0] dout
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);
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genvar i;
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generate
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for (i = 0; i < 3; i = i + 1) begin : row
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inv #(.ID(i)) u_cell (.d(din[i]), .q(dout[i]));
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end
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endgenerate
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generate
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if (N > 0) begin : opt
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wire tap;
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assign tap = din[0];
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end
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endgenerate
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endmodule
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