48 lines
1.0 KiB
Verilog
48 lines
1.0 KiB
Verilog
// Richer Phase 2 test: comb always with case, ternary, continuous
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// assign, and two levels of hierarchy.
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module alu (
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input wire [1:0] op,
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input wire [7:0] a,
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input wire [7:0] b,
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output reg [7:0] y
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);
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always @(*) begin
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case (op)
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2'b00: y = a + b;
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2'b01: y = a - b;
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2'b10: y = a & b;
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default: y = a ^ b;
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endcase
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end
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endmodule
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module datapath (
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input wire [1:0] sel,
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input wire [7:0] x,
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input wire [7:0] z,
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output wire [7:0] result,
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output wire is_zero
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);
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wire [7:0] alu_out;
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alu u_alu (.op(sel), .a(x), .b(z), .y(alu_out));
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assign result = alu_out;
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assign is_zero = (alu_out == 8'b0) ? 1'b1 : 1'b0;
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endmodule
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module chip (
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input wire [1:0] mode,
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input wire [7:0] in0,
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input wire [7:0] in1,
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output wire [7:0] out,
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output wire zero
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);
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datapath u_dp (
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.sel (mode),
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.x (in0),
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.z (in1),
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.result (out),
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.is_zero(zero)
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);
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endmodule
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