82 lines
1.7 KiB
Verilog
82 lines
1.7 KiB
Verilog
// Check that soft packed unions can have members with different widths.
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module test;
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bit failed = 1'b0;
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typedef union soft packed {
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logic [31:0] w;
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logic [15:0] h;
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logic [7:0] b;
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} data_t;
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typedef union soft {
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logic [31:0] w;
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logic [7:0] b;
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} implicit_packed_t;
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typedef union soft packed {
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logic [15:0] w;
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union soft {
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logic [7:0] b;
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logic [3:0] n;
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} part;
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} nested_t;
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data_t data;
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implicit_packed_t implicit_packed;
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nested_t nested;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0h, got %0h", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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initial begin
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data.w = 32'h12345678;
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`check($bits(data), 32);
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`check($bits(data_t), 32);
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`check(data.w, 32'h12345678);
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`check(data.h, 16'h5678);
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`check(data.b, 8'h78);
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data.h = 16'habcd;
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`check(data.w, 32'h1234abcd);
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`check(data.h, 16'habcd);
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`check(data.b, 8'hcd);
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data.b = 8'hef;
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`check(data.w, 32'h1234abef);
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`check(data.h, 16'habef);
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`check(data.b, 8'hef);
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implicit_packed.w = 32'hf0e1d2c3;
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`check($bits(implicit_packed_t), 32);
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`check(implicit_packed.b, 8'hc3);
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implicit_packed.b = 8'h34;
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`check(implicit_packed.w, 32'hf0e1d234);
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nested.w = 16'hbeef;
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`check($bits(nested_t), 16);
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`check($bits(nested.part), 8);
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`check(nested.part.b, 8'hef);
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`check(nested.part.n, 4'hf);
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nested.part.n = 4'ha;
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`check(nested.w, 16'hbeea);
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`check(nested.part.b, 8'hea);
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nested.part.b = 8'h55;
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`check(nested.w, 16'hbe55);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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