34 lines
580 B
Verilog
34 lines
580 B
Verilog
// Check that net declarations can mix initialized and uninitialized entries.
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module test;
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reg failed;
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wire [3:0] a, b = 4'h5;
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wire [3:0] c = 4'ha, d;
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assign a = b;
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assign d = c;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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initial begin
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failed = 1'b0;
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`check(a, 4'h5)
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`check(b, 4'h5)
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`check(c, 4'ha)
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`check(d, 4'ha)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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