30 lines
551 B
Verilog
30 lines
551 B
Verilog
// This protects ordinary partial ANSI port parsing near interface
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// formal grammar.
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//
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// This file is placed into the Public Domain, for any use, without
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// warranty.
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module test;
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logic [3:0] value;
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logic [3:0] result;
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plain dut(value, result);
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initial begin
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value = 4'ha;
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#1;
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if (result !== 4'ha) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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module plain(
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input logic [3:0] value,
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output logic [3:0] result
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);
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assign result = value;
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endmodule
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