44 lines
939 B
Verilog
44 lines
939 B
Verilog
// This tests connecting scalar interface-typed formals to interface
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// array elements selected by generated constant indices.
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interface bus_if ();
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logic [7:0] value;
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modport producer(output value);
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modport consumer(input value);
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endinterface
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module drive(input [7:0] val, bus_if.producer bus);
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assign bus.value = val;
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endmodule
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module sample(output [7:0] y, bus_if.consumer bus);
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assign y = bus.value;
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endmodule
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module test;
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bus_if buses[2]();
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wire [7:0] y[2];
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genvar i;
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generate
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for (i = 0; i < 2; i = i + 1) begin : gen
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localparam [7:0] VAL = 8'd11 + i;
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drive d(VAL, buses[i]);
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sample s(.y(y[i]), .bus(buses[i]));
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end
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endgenerate
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initial begin
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#1;
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if (y[0] !== 8'd11) begin
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$display("FAILED: y[0]=%0d", y[0]);
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$finish;
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end
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if (y[1] !== 8'd12) begin
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$display("FAILED: y[1]=%0d", y[1]);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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