34 lines
685 B
Verilog
34 lines
685 B
Verilog
// This tests connecting a scalar interface-typed formal to one element
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// of an interface instance array.
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interface bus_if ();
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logic [7:0] value;
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modport producer(output value);
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modport consumer(input value);
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endinterface
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module drive(input [7:0] val, bus_if.producer bus);
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assign bus.value = val;
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endmodule
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module sample(output [7:0] y, bus_if.consumer bus);
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assign y = bus.value;
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endmodule
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module test;
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bus_if buses[2]();
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wire [7:0] y;
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drive d0(8'd37, buses[0]);
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sample s0(.bus(buses[0]), .y(y));
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initial begin
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#1;
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if (y !== 8'd37) begin
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$display("FAILED: y=%0d", y);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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