41 lines
688 B
Verilog
41 lines
688 B
Verilog
// Check that multi-dimensional packed vector class properties are supported.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do begin \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0h, got %0h", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end \
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end while (0)
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class C;
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logic [1:0][3:0] x;
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bit [0:1][0:3] y;
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endclass
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C c;
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initial begin
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c = new;
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c.x = 8'h5a;
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c.y = 8'hc3;
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`check(c.x, 8'h5a);
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`check(c.y, 8'hc3);
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c.x += 8'h01;
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c.y ^= 8'hff;
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`check(c.x, 8'h5b);
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`check(c.y, 8'h3c);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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