79 lines
2.1 KiB
Verilog
79 lines
2.1 KiB
Verilog
`begin_keywords "1364-2005"
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module top;
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reg pass = 1'b1;
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reg clk = 0;
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reg [7:0] result;
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reg [3:0] bit;
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integer count;
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always #10 clk = ~clk;
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initial begin
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// Since the bit is not defined this assignment will not happen.
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// We will check to verify this fact 1 time step after it should
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// happen (50).
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#0;
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result[bit] <= repeat(3) @(posedge clk) 1'b0;
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if ($simtime != 0 || result !== 8'bx) begin
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$display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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#51;
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if (result !== 8'hxx) begin
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$display("Failed repeat(3) at %0t, expected 8'hxx, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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bit = 0;
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result[bit] <= @(posedge clk) 4'h0;
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@(result)
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if ($simtime != 70 || result !== 8'bxxxxxxx0) begin
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$display("Failed repeat(3) at %0t, expected 8'bxxxxxxx0, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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// These should execute as if there was no event control
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count = 0;
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result[bit] <= repeat(count) @(posedge clk) 1'b1;
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#1
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if ($simtime != 71 || result !== 8'bxxxxxxx1) begin
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$display("Failed @ at %0t, expected 8'bxxxxxxx1, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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count = -1;
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result[bit+1] <= repeat(count) @(posedge clk) 1'b0;
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#1
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if ($simtime != 72 || result !== 8'bxxxxxx01) begin
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$display("Failed @ at %0t, expected 8'bxxxxxx01, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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result[bit+2] <= repeat(0) @(posedge clk) 1'b1;
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#1
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if ($simtime != 73 || result !== 8'bxxxxx101) begin
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$display("Failed @ at %0t, expected 8'bxxxxx101, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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result[bit+3] <= repeat(-1) @(posedge clk) 1'b0;
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#1
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if ($simtime != 74 || result !== 8'bxxxx0101) begin
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$display("Failed @ at %0t, expected 8'bxxxx0101, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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$finish;
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end
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endmodule
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`end_keywords
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