41 lines
622 B
Verilog
41 lines
622 B
Verilog
`timescale 1ns/1ps
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module tb;
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reg in;
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wire out;
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top dut(out, in);
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initial begin
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$monitor("%.3f: %b %b %b",$realtime,out,dut.intv,in);
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$sdf_annotate("ivltests/br_gh1248.sdf");
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#1;
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in = 1'b0;
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#1;
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in = 1'b1;
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#1;
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in = 1'b0;
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#1;
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end
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endmodule
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module top(output wire out, input wire in);
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wire [2:0] intv;
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assign intv[0] = in;
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buff i1 (.Y(intv[1]), .A(intv[0]));
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buff i2 (.Y(intv[2]), .A(intv[1]));
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assign out = intv[2];
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endmodule
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`celldefine
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module buff(output wire Y, input wire A);
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buf (Y, A);
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specify
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(A => Y) = 0;
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endspecify
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endmodule
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`endcelldefine
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