iverilog/ivtest/gold/pr1866215.gold

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./ivltests/pr1866215.v:31: warning: Port 1 (CH) of module C expects 7 bit(s), given 6.
./ivltests/pr1866215.v:31: : Padding 1 high bits of the port.
./ivltests/pr1866215.v:31: warning: Port 3 (SH) of module C expects 8 bit(s), given 7.
./ivltests/pr1866215.v:31: : Padding 1 high bits of the port.
./ivltests/pr1866215.v:15: warning: Port 1 (CH) of module B expects 6 bit(s), given 7.
./ivltests/pr1866215.v:15: : Padding 1 high bits of the expression.
./ivltests/pr1866215.v:15: warning: Port 3 (SH) of module B expects 7 bit(s), given 8.
./ivltests/pr1866215.v:15: : Padding 1 high bits of the expression.
C1H=33, {C1L, CL}={1555555, zzzzzzZ5}, S1H=66, {S1L, SL}={2aaaaaa, zzzzzzZa}