151 lines
4.6 KiB
C++
151 lines
4.6 KiB
C++
#ifndef __PGate_H
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#define __PGate_H
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/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: PGate.h,v 1.2 1998/12/01 00:42:13 steve Exp $"
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#endif
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# include <vector>
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class PExpr;
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class PUdp;
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class Design;
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/*
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* A PGate represents a Verilog gate. The gate has a name and other
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* properties, and a set of pins that connect to wires. It is known at
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* the time a gate is constructed how many pins the gate has.
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*
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* This pins of a gate are connected to expressions. The elaboration
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* step will need to convert expressions to a network of gates in
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* order to elaborate expression inputs, but that can easily be done.
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*/
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class PGate {
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public:
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explicit PGate(const string&name, const vector<PExpr*>&pins, long del)
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: name_(name), delay_(del), pins_(pins) { }
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virtual ~PGate() { }
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const string& get_name() const { return name_; }
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long get_delay() const { return delay_; }
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unsigned pin_count() const { return pins_.size(); }
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const PExpr*pin(unsigned idx) const { return pins_[idx]; }
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virtual void dump(ostream&out) const;
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virtual void elaborate(Design*des, const string&path) const;
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protected:
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void dump_pins(ostream&out) const;
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private:
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const string name_;
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const unsigned long delay_;
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const vector<PExpr*> pins_;
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private: // not implemented
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PGate(const PGate&);
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PGate& operator= (const PGate&);
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};
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/* A continuous assignment has a single output and a single input. The
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input is passed directly to the output. This is different from a
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BUF because elaboration may need to turn this into a vector of
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gates. */
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class PGAssign : public PGate {
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public:
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explicit PGAssign(const vector<PExpr*>&pins)
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: PGate("", pins, 0) { assert(pins.size() == 2); }
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void dump(ostream&out) const;
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virtual void elaborate(Design*des, const string&path) const;
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private:
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};
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/* The Builtin class is specifically a gate with one of the builtin
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types. The parser recognizes these types during parse. These types
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have special properties that allow them to be treated specially. */
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class PGBuiltin : public PGate {
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public:
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enum Type { AND, NAND, OR, NOR, XOR, XNOR, BUF, BUFIF0, BUFIF1,
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NOT, NOTIF0, NOTIF1, PULLDOWN, PULLUP, NMOS, RNMOS,
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PMOS, RPMOS, CMOS, RCMOS, TRAN, RTRAN, TRANIF0,
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TRANIF1, RTRANIF0, RTRANIF1 };
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public:
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explicit PGBuiltin(Type t, const string&name,
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const vector<PExpr*>&pins, long del = 0)
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: PGate(name, pins, del), type_(t)
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{ }
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Type type() const { return type_; }
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virtual void dump(ostream&out) const;
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virtual void elaborate(Design*, const string&path) const;
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private:
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Type type_;
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};
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/*
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* This kind of gate is an instantiation of a module. The stored type
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* is the name of a module definition somewhere in the pform. This
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* type als handles UDP devices, because it is generally not known at
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* parse time whether a name belongs to a module or a UDP.
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*/
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class PGModule : public PGate {
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public:
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explicit PGModule(const string&type, const string&name,
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const vector<PExpr*>&pins)
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: PGate(name, pins, 0), type_(type) { }
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virtual void dump(ostream&out) const;
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virtual void elaborate(Design*, const string&path) const;
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private:
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string type_;
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void elaborate_mod_(Design*, Module*mod, const string&path) const;
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void elaborate_udp_(Design*, PUdp *udp, const string&path) const;
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};
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/*
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* $Log: PGate.h,v $
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* Revision 1.2 1998/12/01 00:42:13 steve
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* Elaborate UDP devices,
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* Support UDP type attributes, and
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* pass those attributes to nodes that
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* are instantiated by elaboration,
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* Put modules into a map instead of
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* a simple list.
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*
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* Revision 1.1 1998/11/03 23:28:54 steve
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* Introduce verilog to CVS.
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*
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*/
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#endif
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