127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: fpga.c,v 1.2 2001/08/31 02:59:06 steve Exp $"
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#endif
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# include "config.h"
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/*
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* This is a null target module. It does nothing.
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*/
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# include <ivl_target.h>
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# include "fpga_priv.h"
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/* This is the opened xnf file descriptor. It is the output that this
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code generator writes to. */
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FILE*xnf = 0;
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const char*part = 0;
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device_t device = 0;
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extern const struct device_s d_generic;
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static int show_process(ivl_process_t net, void*x)
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{
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fprintf(stderr, "fpga target: unsynthesized behavioral code\n");
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return 0;
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}
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static void show_root_ports(ivl_scope_t root)
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{
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unsigned cnt = ivl_scope_sigs(root);
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unsigned idx;
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for (idx = 0 ; idx < cnt ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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const char*use_name;
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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use_name = ivl_signal_basename(sig);
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if (ivl_signal_pins(sig) == 1) {
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ivl_nexus_t nex = ivl_signal_pin(sig, 0);
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fprintf(xnf, "SIG, %s, PIN=%s\n",
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mangle_nexus_name(nex), use_name);
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} else {
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unsigned pin;
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for (pin = 0 ; pin < ivl_signal_pins(sig); pin += 1) {
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ivl_nexus_t nex = ivl_signal_pin(sig, pin);
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fprintf(xnf, "SIG, %s, PIN=%s%u\n",
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mangle_nexus_name(nex), use_name,
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pin);
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}
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}
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}
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}
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/*
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* This is the main entry point that ivl uses to invoke me, the code
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* generator.
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*/
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int target_design(ivl_design_t des)
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{
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const char*path = ivl_design_flag(des, "-o");
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ivl_scope_t root = ivl_design_root(des);
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xnf = fopen(path, "w");
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if (xnf == 0) {
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perror(path);
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return -1;
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}
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fprintf(xnf, "LCANET,6\n");
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fprintf(xnf, "PROG,iverilog,$Name: $,\"Icarus Verilog/fpga.tgt\"\n");
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part = ivl_design_flag(des, "part");
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if (part && (part[0]!=0)) {
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fprintf(xnf, "PART,%s\n", part);
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}
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device = &d_generic;
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/* Catch any behavioral code that is left, and write warnings
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that it is not supported. */
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ivl_design_process(des, show_process, 0);
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show_root_ports(root);
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/* Scan the scopes, looking for gates to draw into the output
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netlist. */
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show_scope_gates(root, 0);
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fprintf(xnf, "EOF\n");
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return 0;
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}
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/*
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* $Log: fpga.c,v $
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* Revision 1.2 2001/08/31 02:59:06 steve
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* Add root port SIG records.
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*
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* Revision 1.1 2001/08/28 04:14:20 steve
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* Add the fpga target.
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*
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*/
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