393 lines
11 KiB
C++
393 lines
11 KiB
C++
#ifndef __vvm_H
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#define __vvm_H
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/*
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* Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm.h,v 1.25 1999/12/05 02:24:09 steve Exp $"
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#endif
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# include <cassert>
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# include "vpi_priv.h"
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/*
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* The Verilog Virtual Machine are definitions for the virtual machine
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* that executes models that the simulation generator makes.
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*/
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typedef unsigned vvm_u32;
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class vvm_event;
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class vvm_simulation;
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class vvm_simulation_cycle;
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class vvm_thread;
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class ostream;
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inline vpip_bit_t operator & (vpip_bit_t l, vpip_bit_t r)
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{
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if (l == V0) return V0;
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if (r == V0) return V0;
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if ((l == V1) && (r == V1)) return V1;
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return Vx;
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}
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inline vpip_bit_t operator | (vpip_bit_t l, vpip_bit_t r)
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{
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if (l == V1) return V1;
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if (r == V1) return V1;
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if ((l == V0) && (r == V0)) return V0;
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return Vx;
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}
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inline vpip_bit_t operator ^ (vpip_bit_t l, vpip_bit_t r)
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{
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if (l == Vx) return Vx;
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if (l == Vz) return Vx;
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if (r == Vx) return Vx;
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if (r == Vz) return Vx;
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if (l == V0) return r;
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return (r == V0)? V1 : V0;
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}
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inline vpip_bit_t less_with_cascade(vpip_bit_t l, vpip_bit_t r, vpip_bit_t c)
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{
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if (l == Vx) return Vx;
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if (r == Vx) return Vx;
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if (l > r) return V0;
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if (l < r) return V1;
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return c;
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}
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inline vpip_bit_t greater_with_cascade(vpip_bit_t l, vpip_bit_t r, vpip_bit_t c)
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{
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if (l == Vx) return Vx;
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if (r == Vx) return Vx;
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if (l > r) return V1;
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if (l < r) return V0;
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return c;
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}
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extern vpip_bit_t add_with_carry(vpip_bit_t l, vpip_bit_t r, vpip_bit_t&carry);
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inline vpip_bit_t not(vpip_bit_t l)
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{
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switch (l) {
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case V0:
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return V1;
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case V1:
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return V0;
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default:
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return Vx;
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}
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}
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extern bool posedge(vpip_bit_t from, vpip_bit_t to);
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class vvm_bits_t {
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public:
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virtual ~vvm_bits_t() =0;
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virtual unsigned get_width() const =0;
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virtual vpip_bit_t get_bit(unsigned idx) const =0;
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unsigned as_unsigned() const;
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};
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extern ostream& operator << (ostream&os, vpip_bit_t);
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extern ostream& operator << (ostream&os, const vvm_bits_t&str);
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/*
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* The vvm_bitset_t is a fixed width array-like set of vpip_bit_t
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* items. A number is often times made up of bit sets instead of
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* single bits. The fixed array is used when possible because of the
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* more thorough type checking and (hopefully) better optimization.
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*/
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template <unsigned WIDTH> class vvm_bitset_t : public vvm_bits_t {
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public:
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vvm_bitset_t()
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{ for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
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bits[idx] = Vz;
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}
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vvm_bitset_t(const vvm_bits_t&that)
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{ unsigned wid = WIDTH;
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if (that.get_width() < WIDTH)
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wid = that.get_width();
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for (unsigned idx = 0 ; idx < wid ; idx += 1)
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bits[idx] = that.get_bit(idx);
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for (unsigned idx = wid ; idx < WIDTH ; idx += 1)
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bits[idx] = V0;
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}
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vvm_bitset_t(const vvm_bitset_t<WIDTH>&that)
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{ bits = that.bits; }
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vpip_bit_t operator[] (unsigned idx) const { return bits[idx]; }
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vpip_bit_t&operator[] (unsigned idx) { return bits[idx]; }
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unsigned get_width() const { return WIDTH; }
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vpip_bit_t get_bit(unsigned idx) const { return bits[idx]; }
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public:
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vpip_bit_t bits[WIDTH];
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};
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/*
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* Verilog events (update events and nonblocking assign) are derived
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* from this abstract class so that the simulation engine can treat
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* all of them identically.
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*/
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class vvm_event {
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friend class vvm_simulation;
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public:
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vvm_event();
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virtual ~vvm_event() =0;
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virtual void event_function() =0;
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static void callback_(void*);
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private:
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struct vpip_event*event_;
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private: // not implemented
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vvm_event(const vvm_event&);
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vvm_event& operator= (const vvm_event&);
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};
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/*
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* This class is the main simulation engine. Object of this type are
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* self-contained simulations. Generally, only one is needed.
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*/
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class vvm_simulation {
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public:
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vvm_simulation();
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~vvm_simulation();
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// Take a simulation that has been primed with some initial
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// events, and run it. Continue running it until the
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// simulation stops. The sim parameter becomes the new list,
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// or 0 if the events run out. The simulation clock is
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// advanced for the first cycle in sim.
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void run();
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// Add an event to an existing simulation cycle list. If there
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// is not a cycle for the exact delay of the event, create one
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// and insert it into the cycle list. Add the event to the
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// list of events for the cycle time.
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void insert_event(unsigned long delay, vvm_event*event);
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// This puts the event in the current active list. No delay.
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void active_event(vvm_event*event);
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// These are versions of the *_event methods that take
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// vvm_thread objects instead.
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void thread_delay(unsigned long delay, vvm_thread*);
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void thread_active(vvm_thread*);
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// Trigger an event as a monitor event causes it to be
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// scheduled and executed when the time cycle is
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// complete. Unlike other events, the execution of a event so
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// scheduled will not cause the event to be deleted. Also,
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// only one event can be a monitor.
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void monitor_event(vvm_event*);
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bool finished() const;
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private: // not implemented
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vvm_simulation(const vvm_simulation&);
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vvm_simulation& operator= (const vvm_simulation&);
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};
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/*
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* The vvm_signal_t template is the real object that handles the
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* receiving of assignments and doing whatever is done. It also
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* connects VPI to the C++/vvm design.
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*/
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template <unsigned WIDTH> class vvm_signal_t : public __vpiSignal {
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public:
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vvm_signal_t(vvm_bitset_t<WIDTH>*b)
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{ bits = b->bits;
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nbits = WIDTH;
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}
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~vvm_signal_t() { }
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void init_P(unsigned idx, vpip_bit_t val)
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{ bits[idx] = val; }
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void set_P(vvm_simulation*sim, unsigned idx, vpip_bit_t val)
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{ bits[idx] = val;
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vpip_run_value_changes(this);
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}
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void set_P(vvm_simulation*sim, const vvm_bitset_t<WIDTH>&val)
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{ for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
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set(sim, idx, val[idx]);
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}
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};
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struct vvm_ram_callback {
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vvm_ram_callback();
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virtual ~vvm_ram_callback();
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virtual void handle_write(vvm_simulation*sim, unsigned idx) =0;
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vvm_ram_callback*next_;
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};
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template <unsigned WIDTH, unsigned SIZE>
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class vvm_memory_t : public __vpiMemory {
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public:
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vvm_memory_t()
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{ cb_list_ = 0;
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}
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void set_word(vvm_simulation*sim, unsigned addr,
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const vvm_bitset_t<WIDTH>&val)
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{ unsigned base = WIDTH * addr;
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for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
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bits[base+idx] = val[idx];
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call_list_(sim, addr);
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}
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void set_word(vvm_simulation*sim, unsigned addr,
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const vpip_bit_t val[WIDTH])
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{ unsigned base = WIDTH * addr;
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for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
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bits[base+idx] = val[idx];
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call_list_(sim, addr);
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}
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vvm_bitset_t<WIDTH> get_word(unsigned addr) const
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{ vvm_bitset_t<WIDTH> val;
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unsigned base = WIDTH * addr;
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for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
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val[idx] = bits[base+idx];
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return val;
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}
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void set_callback(vvm_ram_callback*ram)
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{ ram->next_ = cb_list_;
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cb_list_ = ram;
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}
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private:
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vvm_ram_callback*cb_list_;
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void call_list_(vvm_simulation*sim, unsigned idx)
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{ for (vvm_ram_callback*cur = cb_list_; cur; cur = cur->next_)
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cur->handle_write(sim, idx);
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}
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};
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/*
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* $Log: vvm.h,v $
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* Revision 1.25 1999/12/05 02:24:09 steve
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* Synthesize LPM_RAM_DQ for writes into memories.
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*
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* Revision 1.24 1999/12/02 03:36:01 steve
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* shiftl and shiftr take unsized second parameter.
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*
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* Revision 1.23 1999/11/22 00:30:52 steve
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* Detemplate some and, or and nor methods.
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*
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* Revision 1.22 1999/11/21 00:13:09 steve
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* Support memories in continuous assignments.
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*
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* Revision 1.21 1999/11/10 02:52:24 steve
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* Create the vpiMemory handle type.
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*
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* Revision 1.20 1999/11/01 02:07:41 steve
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* Add the synth functor to do generic synthesis
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* and add the LPM_FF device to handle rows of
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* flip-flops.
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*
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* Revision 1.19 1999/10/31 04:11:28 steve
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* Add to netlist links pin name and instance number,
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* and arrange in vvm for pin connections by name
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* and instance number.
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*
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* Revision 1.18 1999/10/29 03:37:22 steve
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* Support vpiValueChance callbacks.
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*
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* Revision 1.17 1999/10/28 21:36:00 steve
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* Get rid of monitor_t and fold __vpiSignal into signal.
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*
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* Revision 1.16 1999/10/28 00:47:25 steve
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* Rewrite vvm VPI support to make objects more
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* persistent, rewrite the simulation scheduler
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* in C (to interface with VPI) and add VPI support
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* for callbacks.
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*
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* Revision 1.15 1999/10/13 03:15:51 steve
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* Remove useless operator=.
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*
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* Revision 1.14 1999/10/06 01:28:18 steve
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* The $finish task should work immediately.
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*
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* Revision 1.13 1999/10/05 04:02:10 steve
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* Relaxed width handling for <= assignment.
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*
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* Revision 1.12 1999/09/29 18:36:04 steve
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* Full case support
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*
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* Revision 1.11 1999/09/28 01:13:15 steve
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* Support in vvm > and >= behavioral operators.
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*
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* Revision 1.10 1999/08/15 01:23:56 steve
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* Convert vvm to implement system tasks with vpi.
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*
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* Revision 1.9 1999/06/21 01:02:34 steve
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* Add init to vvm_signal_t.
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*
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* Revision 1.8 1999/06/07 03:40:22 steve
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* Implement the < binary operator.
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*
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* Revision 1.7 1999/05/03 01:51:29 steve
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* Restore support for wait event control.
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*
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* Revision 1.6 1999/04/22 04:56:58 steve
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* Add to vvm proceedural memory references.
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*
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* Revision 1.5 1999/03/16 04:43:46 steve
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* Add some logical operators.
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*
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* Revision 1.4 1999/02/08 03:55:55 steve
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* Do not generate code for signals,
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* instead use the NetESignal node to
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* generate gate-like signal devices.
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*
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* Revision 1.3 1998/12/17 23:54:58 steve
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* VVM support for small sequential UDP objects.
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*
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* Revision 1.2 1998/11/10 00:48:31 steve
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* Add support it vvm target for level-sensitive
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* triggers (i.e. the Verilog wait).
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* Fix display of $time is format strings.
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*
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* Revision 1.1 1998/11/09 23:44:10 steve
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* Add vvm library.
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*
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*/
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#endif
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