299 lines
7.6 KiB
C++
299 lines
7.6 KiB
C++
/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-verilog.cc,v 1.1 1998/11/03 23:29:05 steve Exp $"
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#endif
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/*
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* This rather interesting target generates Verilog from the
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* design. This is interesting since by the time I get here,
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* elaboration and generic optimizations have been performed. This is
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* useful for feeding optimized designs to other tools, or the human
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* for debugging.
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*/
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# include <iostream>
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# include <iomanip>
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# include <strstream>
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# include <typeinfo>
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# include "target.h"
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extern const struct target tgt_verilog;
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class target_verilog : public target_t {
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public:
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virtual void start_design(ostream&os, const Design*);
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virtual void signal(ostream&os, const NetNet*);
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virtual void logic(ostream&os, const NetLogic*);
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virtual void bufz(ostream&os, const NetBUFZ*);
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virtual void start_process(ostream&os, const NetProcTop*);
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virtual void proc_assign(ostream&os, const NetAssign*);
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virtual void proc_block(ostream&os, const NetBlock*);
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virtual void proc_delay(ostream&os, const NetPDelay*);
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virtual void proc_event(ostream&os, const NetPEvent*);
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virtual void proc_task(ostream&os, const NetTask*);
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virtual void end_design(ostream&os, const Design*);
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private:
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unsigned indent_;
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void emit_expr_(ostream&os, const NetExpr*);
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};
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static ostream& operator<< (ostream&o, NetNet::Type t)
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{
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switch (t) {
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case NetNet::WIRE:
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o << "wire";
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break;
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case NetNet::REG:
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o << "reg";
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break;
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}
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return o;
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}
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/*
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* The output of the design starts here. The emit operation calls the
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* design_start and design_end target methods around the scan of the
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* design. Targets can use these hooks to generate header or footer
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* information if desired.
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*/
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void target_verilog::start_design(ostream&os, const Design*)
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{
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indent_ = 0;
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os << "module " << "main" << ";" << endl;
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}
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/*
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* Emit first iterates over all the signals. This gives the target a
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* chance to declare signal variables before the network is assembled
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* or behaviors are written.
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*/
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void target_verilog::signal(ostream&os, const NetNet*net)
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{
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os << " " << net->type();
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if (net->pin_count() > 1)
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os << " [" << net->msb() << ":" << net->lsb() << "]";
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if (net->delay1())
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os << " #" << net->delay1();
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os << " " << mangle(net->name()) << ";" << endl;
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}
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void target_verilog::logic(ostream&os, const NetLogic*net)
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{
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switch (net->type()) {
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case NetLogic::AND:
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os << " and";
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break;
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case NetLogic::NAND:
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os << " nand";
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break;
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case NetLogic::NOR:
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os << " nor";
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break;
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case NetLogic::NOT:
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os << " not";
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break;
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case NetLogic::OR:
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os << " or";
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break;
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case NetLogic::XOR:
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os << " xor";
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break;
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}
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os << " #" << net->delay1() << " " << mangle(net->name()) << "(";
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unsigned sidx;
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const NetNet*sig = find_link_signal(net, 0, sidx);
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os << mangle(sig->name()) << "[" << sidx << "]";
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for (unsigned idx = 1 ; idx < net->pin_count() ; idx += 1) {
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sig = find_link_signal(net, idx, sidx);
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assert(sig);
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os << ", " << mangle(sig->name()) << "[" << sidx << "]";
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}
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os << ");" << endl;
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}
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void target_verilog::bufz(ostream&os, const NetBUFZ*net)
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{
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assert( net->pin_count() == 2 );
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os << " assign ";
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unsigned sidx;
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const NetNet*sig = find_link_signal(net, 0, sidx);
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os << mangle(sig->name()) << "[" << sidx << "] = ";
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sig = find_link_signal(net, 1, sidx);
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os << mangle(sig->name()) << "[" << sidx << "];" << endl;
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}
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void target_verilog::start_process(ostream&os, const NetProcTop*proc)
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{
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switch (proc->type()) {
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case NetProcTop::KINITIAL:
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os << " initial" << endl;
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break;
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case NetProcTop::KALWAYS:
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os << " always" << endl;
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break;
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}
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indent_ = 6;
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}
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void target_verilog::proc_assign(ostream&os, const NetAssign*net)
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{
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os << setw(indent_) << "";
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const NetNet*lval = net->lval();
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os << mangle(lval->name()) << " = ";
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emit_expr_(os, net->rval());
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os << ";" << endl;
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}
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void target_verilog::emit_expr_(ostream&os, const NetExpr*expr)
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{
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if (const NetEConst*pp = dynamic_cast<const NetEConst*>(expr)) {
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os << pp->value();
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} else if (const NetEIdent*pp = dynamic_cast<const NetEIdent*>(expr)) {
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os << mangle(pp->name());
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} else if (const NetEUnary*pp = dynamic_cast<const NetEUnary*>(expr)) {
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os << pp->op() << "(";
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emit_expr_(os, pp->expr());
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os << ")";
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} else {
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os << "(huh?)";
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}
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}
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void target_verilog::proc_block(ostream&os, const NetBlock*net)
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{
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os << setw(indent_) << "" << "begin" << endl;
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indent_ += 4;
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net->emit_recurse(os, this);
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indent_ -= 4;
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os << setw(indent_) << "" << "end" << endl;
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}
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void target_verilog::proc_delay(ostream&os, const NetPDelay*net)
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{
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os << setw(indent_) << "" << "#" << net->delay() << endl;
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indent_ += 4;
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net->emit_proc_recurse(os, this);
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indent_ -= 4;
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}
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void target_verilog::proc_event(ostream&os, const NetPEvent*net)
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{
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os << setw(indent_) << "" << "@";
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unsigned sidx;
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const NetNet*sig = find_link_signal(net, 0, sidx);
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switch (net->edge()) {
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case NetPEvent::ANYEDGE:
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os << mangle(sig->name()) << "[" << sidx << "]";
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break;
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case NetPEvent::POSEDGE:
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os << "(posedge " << mangle(sig->name()) << "[" << sidx << "])";
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break;
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case NetPEvent::NEGEDGE:
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os << "(negedge " << mangle(sig->name()) << "[" << sidx << "])";
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break;
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}
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os << endl;
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indent_ += 4;
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net->emit_proc_recurse(os, this);
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indent_ -= 4;
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}
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static void vtask_parm(ostream&os, const NetExpr*ex)
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{
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if (const NetEConst*pp = dynamic_cast<const NetEConst*>(ex)) {
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if (pp->value().is_string())
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os << "\"" << pp->value().as_string() << "\"";
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else
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os << pp->value();
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} else if (const NetEIdent*pp = dynamic_cast<const NetEIdent*>(ex)) {
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os << mangle(pp->name());
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} else {
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}
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}
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void target_verilog::proc_task(ostream&os, const NetTask*net)
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{
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os << setw(indent_) << "" << net->name();
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if (net->nparms() > 0) {
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os << "(";
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vtask_parm(os, net->parm(0));
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for (unsigned idx = 1 ; idx < net->nparms() ; idx += 1) {
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os << ", ";
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vtask_parm(os, net->parm(idx));
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}
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os << ")";
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}
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os << ";" << endl;
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}
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/*
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* All done with the design. Flush any output that I've been holding
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* off, and write the footers for the target.
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*/
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void target_verilog::end_design(ostream&os, const Design*)
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{
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os << "endmodule" << endl;
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}
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static target_verilog tgt_verilog_obj;
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const struct target tgt_verilog = {
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"verilog",
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&tgt_verilog_obj
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};
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/*
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* $Log: t-verilog.cc,v $
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* Revision 1.1 1998/11/03 23:29:05 steve
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* Introduce verilog to CVS.
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*
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*/
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