164 lines
4.0 KiB
C++
164 lines
4.0 KiB
C++
/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: Module.cc,v 1.9 2000/01/09 20:37:57 steve Exp $"
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#endif
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# include "Module.h"
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# include "PGate.h"
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# include "PWire.h"
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# include <assert.h>
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Module::Module(const string&name, const svector<Module::port_t*>*pp)
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: name_(name)
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{
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if (pp) {
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// Save the list of ports, then scan the list to make
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// the implicit wires. Add those wires to the wire map.
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ports_ = *pp;
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for (unsigned idx = 0 ; idx < ports_.count() ; idx += 1) {
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port_t*cur = ports_[idx];
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if (cur == 0)
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continue;
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// The port can actually be a list of wires, to
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// remember to scan the set. Also note the case
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// where a wire may be connected to multiple
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// ports, and reuse the link if that happens.
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for (unsigned jdx = 0; jdx < cur->wires.count(); jdx += 1) {
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PWire*tmp = add_wire(cur->wires[jdx]);
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if (tmp != cur->wires[jdx]) {
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delete cur->wires[jdx];
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cur->wires[jdx] = tmp;
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}
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}
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}
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}
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}
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void Module::add_gate(PGate*gate)
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{
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gates_.push_back(gate);
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}
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void Module::add_task(const string&name, PTask*task)
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{
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tasks_[name] = task;
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}
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void Module::add_function(const string &name, PFunction *func)
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{
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funcs_[name] = func;
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}
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PWire* Module::add_wire(PWire*wire)
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{
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PWire*&ep = wires_[wire->name()];
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if (ep) return ep;
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assert(ep == 0);
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ep = wire;
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return wire;
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}
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void Module::add_behavior(PProcess*b)
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{
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behaviors_.push_back(b);
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}
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unsigned Module::port_count() const
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{
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return ports_.count();
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}
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const svector<PWire*>& Module::get_port(unsigned idx) const
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{
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assert(idx < ports_.count());
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return ports_[idx]->wires;
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}
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unsigned Module::find_port(const string&name) const
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{
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assert(name != "");
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for (unsigned idx = 0 ; idx < ports_.count() ; idx += 1)
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if (ports_[idx]->name == name)
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return idx;
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return ports_.count();
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}
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PWire* Module::get_wire(const string&name) const
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{
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map<string,PWire*>::const_iterator obj = wires_.find(name);
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if (obj == wires_.end())
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return 0;
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else
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return (*obj).second;
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}
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PGate* Module::get_gate(const string&name)
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{
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for (list<PGate*>::iterator cur = gates_.begin()
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; cur != gates_.end()
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; cur ++ ) {
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if ((*cur)->get_name() == name)
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return *cur;
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}
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return 0;
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}
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/*
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* $Log: Module.cc,v $
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* Revision 1.9 2000/01/09 20:37:57 steve
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* Careful with wires connected to multiple ports.
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*
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* Revision 1.8 1999/12/11 05:45:41 steve
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* Fix support for attaching attributes to primitive gates.
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*
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* Revision 1.7 1999/09/17 02:06:25 steve
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* Handle unconnected module ports.
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*
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* Revision 1.6 1999/08/04 02:13:02 steve
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* Elaborate module ports that are concatenations of
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* module signals.
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*
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* Revision 1.5 1999/08/03 04:14:49 steve
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* Parse into pform arbitrarily complex module
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* port declarations.
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*
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* Revision 1.4 1999/07/31 19:14:47 steve
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* Add functions up to elaboration (Ed Carter)
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*
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* Revision 1.3 1999/07/03 02:12:51 steve
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* Elaborate user defined tasks.
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*
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* Revision 1.2 1999/06/17 05:34:42 steve
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* Clean up interface of the PWire class,
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* Properly match wire ranges.
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*
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* Revision 1.1 1998/11/03 23:28:51 steve
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* Introduce verilog to CVS.
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*
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*/
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