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<span>View Source</span></a><a role="menuitem" href="https://chatgpt.com/?hints=search&q=Read%20https%3A//raw.githubusercontent.com/steveicarus/iverilog/refs/heads/master/Documentation/developer/guide/misc/xilinx-hint.rst.txt%20so%20I%20can%20ask%20questions%20about%20it." target="_blank" rel="nofollow">
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<span>Open in ChatGPT</span>
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<section id="xilinx-hint">
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<h1>Xilinx Hint<a class="headerlink" href="#xilinx-hint" title="Link to this heading">¶</a></h1>
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||
<p>For those of you who wish to use Icarus Verilog, in combination with
|
||
the Xilinx back end (Foundation or Alliance), it can be done. I have
|
||
run some admittedly simple (2300 equivalent gates) designs through this
|
||
setup, targeting a Spartan XCS10.</p>
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<section id="verilog">
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||
<h2>Verilog:<a class="headerlink" href="#verilog" title="Link to this heading">¶</a></h2>
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||
<p>Older versions of Icarus Verilog (like 19990814) couldn’t synthesize
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||
logic buried in procedural (flip-flop) assignment. Newer versions
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||
(like 20000120) don’t have this limitation.</p>
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||
<p>Procedural assignments have to be given one at a time, to be
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||
“found” by xnfsyn. Say</p>
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||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">always @ (posedge Clk) Y = newY;
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</span><span data-line="2">always @ (posedge Clk) Z = newZ;
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||
</span></pre></div>
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||
</div>
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||
<p>rather than</p>
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||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">always @ (posedge Clk) begin
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||
</span><span data-line="2"> Y = newY;
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||
</span><span data-line="3"> Z = newZ;
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||
</span><span data-line="4">end
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||
</span></pre></div>
|
||
</div>
|
||
<p>Steve’s xnf.txt covers most buffer and pin constructs, but I had reason
|
||
to use a global clock net not connected to an input pin. The standard
|
||
Verilog for a buffer, combined with a declaration to turn that into a
|
||
BUFG, is:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">buf BUFG( your_output_here, your_input_here );
|
||
</span><span data-line="2">$attribute(BUFG,"XNF-LCA","BUFG:O,I")
|
||
</span></pre></div>
|
||
</div>
|
||
<p>I use post-processing on my .xnf files to add “FAST” attributes to
|
||
output pins.</p>
|
||
</section>
|
||
<section id="running-ivl">
|
||
<h2>Running ivl:<a class="headerlink" href="#running-ivl" title="Link to this heading">¶</a></h2>
|
||
<p>The -F switches are important. The following order seems to robustly
|
||
generate valid XNF files, and is used by “verilog -X”:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">-Fsynth -Fnodangle -Fxnfio
|
||
</span></pre></div>
|
||
</div>
|
||
</section>
|
||
<section id="generating-pcf-files">
|
||
<h2>Generating .pcf files:<a class="headerlink" href="#generating-pcf-files" title="Link to this heading">¶</a></h2>
|
||
<p>The ngdbuild step seems to lose pin placement information that ivl
|
||
puts in the XNF file. Use xnf2pcf to extract this information to
|
||
a .pcf file, which the Xilinx place-and-route software _will_ pay
|
||
attention to. Steve says he now makes that information available
|
||
in an NCF file, with -fncf=<path>, but I haven’t tested that.</p>
|
||
<p>Running the Xilinx back end:</p>
|
||
<p>You can presumably use the GUI, but that doesn’t fit in Makefiles :-).
|
||
Here is the command sequence in pseudo-shell-script:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">ngdbuild -p $part $1.xnf $1.ngd
|
||
</span><span data-line="2">map -p $part -o map.ncd $1.ngd
|
||
</span><span data-line="3">xnf2pcf <$1.xnf >$1.pcf # see above
|
||
</span><span data-line="4">par -w -ol 2 -d 0 map.ncd $1.ncd $1.pcf
|
||
</span><span data-line="5">bitgen_flags = -g ConfigRate:SLOW -g TdoPin:PULLNONE -g DonePin:PULLUP \
|
||
</span><span data-line="6"> -g CRC:enable -g StartUpClk:CCLK -g SyncToDone:no \
|
||
</span><span data-line="7"> -g DoneActive:C1 -g OutputsActive:C3 -g GSRInactive:C4 \
|
||
</span><span data-line="8"> -g ReadClk:CCLK -g ReadCapture:enable -g ReadAbort:disable
|
||
</span><span data-line="9">bitgen $1.ncd -l -w $bitgen_flags
|
||
</span></pre></div>
|
||
</div>
|
||
<p>The Xilinx software has diarrhea of the temp files (14, not including
|
||
.xnf, .pcf, .ngd, .ncd, and .bit), so this sequence is best done in a
|
||
dedicated directory. Note in particular that map.ncd is a generic name.</p>
|
||
<p>I had reason to run this remotely (and transparently within a Makefile)
|
||
via ssh. I use the gmake rule:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">%.bit : %.xnf
|
||
</span><span data-line="2"> ssh -x -a -o 'BatchMode yes' ${ALLIANCE_HOST} \
|
||
</span><span data-line="3"> remote_alliance ${REMOTE_DIR} $(basename $@) 2>&1 < $<
|
||
</span><span data-line="4">scp ${ALLIANCE_HOST}:${REMOTE_DIR}/$@ .
|
||
</span></pre></div>
|
||
</div>
|
||
<p>and the remote_alliance script (on ${ALLIANCE_HOST}):</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">/bin/csh
|
||
</span><span data-line="2">cd $1
|
||
</span><span data-line="3">cat >! $2.xnf
|
||
</span><span data-line="4">xnf2pcf <$2.xnf >! $2.pcf
|
||
</span><span data-line="5">./backend $2
|
||
</span></pre></div>
|
||
</div>
|
||
<p>There is now a “Xilinx on Linux HOWTO” at <a class="reference external" href="http://www.polybus.com/xilinx_on_linux.html">http://www.polybus.com/xilinx_on_linux.html</a>
|
||
I haven’t tried this yet, it looks interesting.</p>
|
||
</section>
|
||
<section id="downloading">
|
||
<h2>Downloading:<a class="headerlink" href="#downloading" title="Link to this heading">¶</a></h2>
|
||
<p>I use the XESS (<a class="reference external" href="http://www.xess.com/">http://www.xess.com/</a>) XSP-10 development board, which
|
||
uses the PC parallel (printer) port for downloading and interaction
|
||
with the host. They made an old version of their download program
|
||
public domain, posted it at <a class="reference external" href="http://www.xess.com/FPGA/xstools.zip">http://www.xess.com/FPGA/xstools.zip</a> ,
|
||
and now there is a Linux port at <a class="reference external" href="ftp://ftp.microux.com/pub/pilotscope/xstools.tar.gz">ftp://ftp.microux.com/pub/pilotscope/xstools.tar.gz</a> .</p>
|
||
<p>The above hints are based on my experience with Foundation 1.5 on NT
|
||
(gack) and Alliance 2.1i on Solaris. Your mileage may vary. Good luck!</p>
|
||
<blockquote>
|
||
<div><ul class="simple">
|
||
<li><dl class="simple">
|
||
<dt>Larry Doolittle <<a class="reference external" href="mailto:LRDoolittle%40lbl.gov">LRDoolittle<span>@</span>lbl<span>.</span>gov</a>> August 19, 1999</dt><dd><p>updated February 1, 2000</p>
|
||
</dd>
|
||
</dl>
|
||
</li>
|
||
</ul>
|
||
</div></blockquote>
|
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