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<div class="globaltoc" data-expand-depth="0"><p class="caption" role="heading" aria-level="3"><span class="caption-text">Contents:</span></p>
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<li class="toctree-l1"><a class="reference internal" href="../../releases/index.html">Icarus Verilog Release Notes</a><ul>
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<li class="toctree-l2"><a class="reference internal" href="../../releases/v13-0-release-note.html">🎉 Release V13.0</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/getting_started.html">Getting Started With Icarus Verilog</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/simulation.html">Simulation Using Icarus Verilog</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/command_line_flags.html">iverilog Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/command_files.html">Command File Format</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/verilog_attributes.html">Verilog Attributes</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/ivlpp_flags.html">IVLPP - IVL Preprocessor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/vvp_flags.html">VVP Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/vvp_debug.html">VVP Interactive Mode</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/vvp_library.html">VVP as a library</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/vhdlpp_flags.html">vhdlpp Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/waveform_viewer.html">Viewing Waveforms</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/vpi.html">Using VPI</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/icarus_verilog_extensions.html">Icarus Verilog Extensions</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/icarus_verilog_quirks.html">Icarus Verilog Quirks</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../usage/reporting_issues.html">Reporting Issues</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../../targets/index.html">The Icarus Verilog Targets</a><ul>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-stub.html">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-null.html">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-vlog95.html">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-sizer.html">The sizer Code Analyzer (-tsizer)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../targets/tgt-blif.html">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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</li>
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<li class="toctree-l1 current"><a class="reference internal" href="../index.html">Icarus Verilog Developer Support</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="../getting_started.html">Getting Started as a Contributor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../regression_tests.html">The Regression Test Suite</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../version_stamps.html">Files With Version Information</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">Developer Guide</a><ul>
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<li class="toctree-l3"><a class="reference internal" href="ivl/index.html">IVL - The Core Compiler</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="ivl/netlist.html">Netlist Format</a></li>
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<li class="toctree-l4"><a class="reference internal" href="ivl/attributes.html">Icarus Verilog Attributes</a></li>
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<li class="toctree-l4"><a class="reference internal" href="ivl/ivl_target.html">Loadable Target API (ivl_target)</a></li>
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<li class="toctree-l4"><a class="reference internal" href="ivl/lpm.html">What Is LPM</a></li>
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<li class="toctree-l4"><a class="reference internal" href="ivl/t-dll.html">Loadable Targets</a></li>
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</ul>
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</li>
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<li class="toctree-l3"><a class="reference internal" href="vvp/index.html">VVP - Verilog Virtual Processor</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="vvp/vvp.html">VVP Simulation Engine</a></li>
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<li class="toctree-l4"><a class="reference internal" href="vvp/opcodes.html">Executable Instruction Opcodes</a></li>
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<li class="toctree-l4"><a class="reference internal" href="vvp/vpi.html">VPI Within VVP</a></li>
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<li class="toctree-l4"><a class="reference internal" href="vvp/vthread.html">Thread Details</a></li>
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<li class="toctree-l4"><a class="reference internal" href="vvp/debug.html">Debug Aids For VVP</a></li>
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</ul>
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</li>
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<li class="toctree-l3"><a class="reference internal" href="tgt-vvp/tgt-vvp.html">The VVP Target</a></li>
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<li class="toctree-l3"><a class="reference internal" href="vpi/index.html">VPI in Icarus Verilog</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="vpi/vpi.html">VPI Modules in Icarus Verilog</a></li>
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<li class="toctree-l4"><a class="reference internal" href="vpi/va_math.html">Verilog-A math library</a></li>
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</ul>
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</li>
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<li class="toctree-l3"><a class="reference internal" href="cadpli/cadpli.html">Cadence PLI1 Modules</a></li>
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<li class="toctree-l3"><a class="reference internal" href="misc/index.html">Miscellaneous</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="misc/ieee1364-notes.html">IEEE1364 Notes</a></li>
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<li class="toctree-l4"><a class="reference internal" href="misc/swift.html">Swift Model Support (Preliminary)</a></li>
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<li class="toctree-l4"><a class="reference internal" href="misc/xilinx-hint.html">Xilinx Hint</a></li>
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</ul>
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</li>
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</ul>
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<li class="toctree-l2"><a class="reference internal" href="../glossary.html">Glossary</a></li>
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<li><a class="reference internal" href="#compiler-components">Compiler Components</a></li>
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<li><a class="reference internal" href="#runtime-components">Runtime Components</a></li>
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<span>View Source</span></a><a role="menuitem" href="https://chatgpt.com/?hints=search&q=Read%20https%3A//raw.githubusercontent.com/steveicarus/iverilog/refs/heads/master/Documentation/developer/guide/index.rst.txt%20so%20I%20can%20ask%20questions%20about%20it." target="_blank" rel="nofollow">
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</div><article class="yue" role="main">
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<section id="developer-guide">
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<h1>Developer Guide<a class="headerlink" href="#developer-guide" title="Link to this heading">¶</a></h1>
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||
<p>The developer guide is intended to give you a gross structure of the
|
||
Icarus Verilog compiler source. This will help orient you to the
|
||
source code itself, so that you can find the global parts where you
|
||
can look for even better detail.</p>
|
||
<p>The documentation for getting, building and installing Icarus Verilog
|
||
is kept and maintained at <a class="reference internal" href="../getting_started.html"><span class="doc">Getting Started as a Contributor</span></a></p>
|
||
<p>See the Installation Guide for getting the current source from the git
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||
repository (and how to use the git repository) and see the Developer Guide
|
||
for instructions on participating in the Icarus Verilog development process.
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||
That information will not be repeated here.</p>
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||
<p>Scroll down to a listing with further readings.</p>
|
||
<section id="compiler-components">
|
||
<h2>Compiler Components<a class="headerlink" href="#compiler-components" title="Link to this heading">¶</a></h2>
|
||
<ul class="simple">
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||
<li><p>The compiler driver (driver/)</p></li>
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||
</ul>
|
||
<p>This is the binary that is installed as “iverilog”. This program takes
|
||
the command line arguments and assembles invocations of all the other
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||
subcommands to perform the steps of compilation.</p>
|
||
<ul class="simple">
|
||
<li><p>The preprocessor (ivlpp/)</p></li>
|
||
</ul>
|
||
<p>This implements the Verilog pre-processor. In Icarus Verilog, the
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||
compiler directives `define, `include, `ifdef and etc. are implemented
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||
in an external program. The ivlpp/ directory contains the source for
|
||
this program.</p>
|
||
<ul class="simple">
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||
<li><p>The core compiler (root directory)</p></li>
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||
</ul>
|
||
<p>The “ivl” program is the core that does all the Verilog compiler
|
||
processing that is not handled elsewhere. This is the main core of the
|
||
Icarus Verilog compiler, not the runtime. See below for more details
|
||
on the core itself.</p>
|
||
<ul class="simple">
|
||
<li><p>The loadable code generators (tgt-*/)</p></li>
|
||
</ul>
|
||
<p>This core compiler, after it is finished with parsing and semantic
|
||
analysis, uses loadable code generators to emit code for supported
|
||
targets. The tgt-*/ directories contains the source for the target
|
||
code generators that are bundled with Icarus Verilog. The tgt-vvp/
|
||
directory in particular contains the code generator for the vvp
|
||
runtime.</p>
|
||
</section>
|
||
<section id="runtime-components">
|
||
<h2>Runtime Components<a class="headerlink" href="#runtime-components" title="Link to this heading">¶</a></h2>
|
||
<ul class="simple">
|
||
<li><p>The vvp runtime (vvp/)</p></li>
|
||
</ul>
|
||
<p>This program implements the runtime environment for Icarus
|
||
Verilog. It implements the “vvp” command described in the user
|
||
documentation. See the vvp/ subdirectory for further developer
|
||
documentation.</p>
|
||
<ul class="simple">
|
||
<li><p>The system tasks implementations (vpi/)</p></li>
|
||
</ul>
|
||
<p>The standard Verilog system tasks are implemented using VPI (PLI-2)
|
||
and the source is in this subdirectory.</p>
|
||
<ul class="simple">
|
||
<li><p>The PLI-1 compatibility library (libveriuser/)</p></li>
|
||
</ul>
|
||
<p>The Icarus Verilog support for the deprecated PLI-1 is in this
|
||
subdirectory. The vvp runtime does not directly support the
|
||
PLI-1. Instead, the libveriuser library emulates it using the builtin
|
||
PLI-2 support.</p>
|
||
<ul class="simple">
|
||
<li><p>The Cadence PLI module compatibility module (cadpli/)</p></li>
|
||
</ul>
|
||
<p>It is possible in some specialized situations to load and execute
|
||
PLI-1 code written for Verilog-XL. This directory contains the source
|
||
for the module that provides the Cadence PLI interface.</p>
|
||
</section>
|
||
<section id="the-core-compiler">
|
||
<h2>The Core Compiler<a class="headerlink" href="#the-core-compiler" title="Link to this heading">¶</a></h2>
|
||
<p>The “ivl” binary is the core compiler that does the heavy lifting of
|
||
compiling the Verilog source (including libraries) and generating the
|
||
output. This is the most complex component of the Icarus Verilog
|
||
compilation system.</p>
|
||
<p>The process in the abstract starts with the Verilog lexical analysis
|
||
and parsing to generate an internal “pform”. The pform is then
|
||
translated by elaboration into the “netlist” form. The netlist is
|
||
processed by some functors (which include some optimizations and
|
||
optional synthesis) then is translated into the ivl_target internal
|
||
form. And finally, the ivl_target form is passed via the ivl_target.h
|
||
API to the code generators.</p>
|
||
<ul class="simple">
|
||
<li><p>Lexical Analysis</p></li>
|
||
</ul>
|
||
<p>Lexical analysis and parsing use the tools “flex”, “gperf”, and
|
||
“bison”. The “flex” input file “lexor.lex” recognizes the tokens in
|
||
the input stream. This is called “lexical analysis”. The lexical
|
||
analyzer also does some processing of compiler directives that are not
|
||
otherwise taken care of by the external preprocessor. The lexical
|
||
analyzer uses a table of keywords that is generated using the “gperf”
|
||
program and the input file “lexor_keywords.gperf”. This table allows
|
||
the lexical analyzer to efficiently check input words with the rather
|
||
large set of potential keywords.</p>
|
||
<ul class="simple">
|
||
<li><p>Parsing</p></li>
|
||
</ul>
|
||
<p>The parser input file “parse.y” is passed to the “bison” program to
|
||
generate the parser. The parser uses the functions in parse*.h,
|
||
parse*.cc, pform.h, and pform*.cc to generate the pform from the
|
||
stream of input tokens. The pform is what compiler writers call a
|
||
“decorated parse tree”.</p>
|
||
<p>The pform itself is described by the classes in the header files
|
||
“PScope.h”, “Module.h”, “PGenerate.h”, “Statement.h”, and
|
||
“PExpr.h”. The implementations of the classes in those header files
|
||
are in the similarly named C++ files.</p>
|
||
<ul class="simple">
|
||
<li><p>Elaboration</p></li>
|
||
</ul>
|
||
<p>Elaboration transforms the pform to the netlist form. Elaboration is
|
||
conceptually divided into several major steps: Scope elaboration,
|
||
parameter overrides and defparam propagation, signal elaboration, and
|
||
statement and expression elaboration.</p>
|
||
<p>The elaboration of scopes and parameter overrides and defparam
|
||
propagation are conceptually separate, but are in practice
|
||
intermingled. The elaboration of scopes scans the pform to find and
|
||
instantiate all the scopes of the design. New scopes are created by
|
||
instantiation of modules (starting with the root instances) by user
|
||
defined tasks and functions, named blocks, and generate schemes. The
|
||
elaborate_scope methods implement scope elaboration, and the
|
||
elab_scope.cc source file has the implementations of those
|
||
methods.</p>
|
||
<p>The elaborate.cc source file contains the initial calls to the
|
||
elaborate_scope for the root scopes to get the process started. In
|
||
particular, see the “elaborate” function near the bottom of the
|
||
elaborate.cc source file. The calls to Design::make_root_scope create
|
||
the initial root scopes, and the creation and enqueue of the
|
||
elaborate_root_scope_t work items primes the scope elaboration work
|
||
list.</p>
|
||
<p>Intermingled in the work list are defparms work items that call the
|
||
Design::run_defparams and Design::evaluate_parameters methods that
|
||
override and evaluate parameters. The override and evaluation of
|
||
parameters must be intermingled with the elaboration of scopes because
|
||
the exact values of parameters may impact the scopes created (imagine
|
||
generate schemes and instance arrays) and the created scopes in turn
|
||
create new parameters that need override and evaluation.</p>
|
||
</section>
|
||
<section id="further-reading">
|
||
<h2>Further Reading<a class="headerlink" href="#further-reading" title="Link to this heading">¶</a></h2>
|
||
<p>For further information on the individual parts of Icarus Verilog, see this listing:</p>
|
||
<div class="toctree-wrapper compound">
|
||
<ul>
|
||
<li class="toctree-l1"><a class="reference internal" href="ivl/index.html">IVL - The Core Compiler</a><ul>
|
||
<li class="toctree-l2"><a class="reference internal" href="ivl/netlist.html">Netlist Format</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="ivl/attributes.html">Icarus Verilog Attributes</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="ivl/ivl_target.html">Loadable Target API (ivl_target)</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="ivl/lpm.html">What Is LPM</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="ivl/t-dll.html">Loadable Targets</a></li>
|
||
</ul>
|
||
</li>
|
||
<li class="toctree-l1"><a class="reference internal" href="vvp/index.html">VVP - Verilog Virtual Processor</a><ul>
|
||
<li class="toctree-l2"><a class="reference internal" href="vvp/vvp.html">VVP Simulation Engine</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="vvp/opcodes.html">Executable Instruction Opcodes</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="vvp/vpi.html">VPI Within VVP</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="vvp/vthread.html">Thread Details</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="vvp/debug.html">Debug Aids For VVP</a></li>
|
||
</ul>
|
||
</li>
|
||
<li class="toctree-l1"><a class="reference internal" href="tgt-vvp/tgt-vvp.html">The VVP Target</a></li>
|
||
<li class="toctree-l1"><a class="reference internal" href="vpi/index.html">VPI in Icarus Verilog</a><ul>
|
||
<li class="toctree-l2"><a class="reference internal" href="vpi/vpi.html">VPI Modules in Icarus Verilog</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="vpi/va_math.html">Verilog-A math library</a></li>
|
||
</ul>
|
||
</li>
|
||
<li class="toctree-l1"><a class="reference internal" href="cadpli/cadpli.html">Cadence PLI1 Modules</a></li>
|
||
<li class="toctree-l1"><a class="reference internal" href="misc/index.html">Miscellaneous</a><ul>
|
||
<li class="toctree-l2"><a class="reference internal" href="misc/ieee1364-notes.html">IEEE1364 Notes</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="misc/swift.html">Swift Model Support (Preliminary)</a></li>
|
||
<li class="toctree-l2"><a class="reference internal" href="misc/xilinx-hint.html">Xilinx Hint</a></li>
|
||
</ul>
|
||
</li>
|
||
</ul>
|
||
</div>
|
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</section>
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