30 lines
516 B
Verilog
30 lines
516 B
Verilog
// Check that sequential block prefix labels work.
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module test;
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reg failed;
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reg value;
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initial begin
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failed = 1'b0;
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value = 1'b0;
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BLOCK_LABEL: (* keep = 1 *) begin
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value = 1'b1;
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disable BLOCK_LABEL;
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value = 1'b0;
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end : BLOCK_LABEL
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if (value !== 1'b1) begin
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$display("FAILED(%0d). Block prefix label did not create a named scope",
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`__LINE__);
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failed = 1'b1;
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end
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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