36 lines
1.1 KiB
ReStructuredText
36 lines
1.1 KiB
ReStructuredText
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Verilog Attributes
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==================
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This is a description of the various attributes that the Icarus Verilog tools
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understand. The attributes are attached to objects using the "(* ... *)"
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syntax, which is described by the Verilog LRM.
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Attributes that start with "ivl_" are Icarus Verilog specific are are probably
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ignored by other tools.
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Optimizations
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-------------
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* ivl_do_not_elide (snapshot 20140619 or later)
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This applies to signals (i.e. reg, wire, etc.) and tells the optimizer to
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not elide the signal, even if it is not referenced anywhere in the
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design. This is useful if the signal is for some reason only accessed by
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VPI/PLI code.
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Synthesis
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---------
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* ivl_synthesis_cell
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Applied to a module definition, this tells the synthesizer that the module
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is a cell. The synthesizer does not descend into synthesis cells, as they
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are assumed to be primitives in the target technology.
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* ivl_synthesis_off
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Attached to an "always" statement, this tells the synthesizer that the
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statement is not to be synthesized. This may be useful, for example, to tell
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the compiler that a stretch of code is test-bench code.
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