steve 2dedd6c067 Scopes and processes are accessible randomly from ... the design, and signals and logic are accessible from scopes. Remove the target calls that are no longer needed. Add the ivl_nexus_ptr_t and the means to get at them from nexus objects. Give names to methods that manipulate the ivl_design_t type more consistent names.		2000-10-15 04:46:23 +00:00
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.cvsignore	Add enough tgt-verilog code to support hello world.	2000-09-23 05:15:07 +00:00
Makefile.in	Fix the clean target and excess dependencies.	2000-10-04 17:08:31 +00:00
verilog.c	Scopes and processes are accessible randomly from	2000-10-15 04:46:23 +00:00