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iverilog/tgt-vhdl
Nick Gasson c81645ff46 tgt-vhdl: Fix expression generation corner case and bug in xnor reduction operator
Certain types of expressions involving only constants would produce
ambiguous VHDL output. Fixed by qualifying one of the arguments. E.g.

   ('0' or '1') = '1'

Which is ambiguous becomes

   (std_logic'('0') or '1') = '1'

This fixes the xnor_test test.

Reduce XNOR was implemented incorrectly because of trivial typo
2011-04-06 19:20:25 -07:00
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