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By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
15 lines
387 B
Verilog
15 lines
387 B
Verilog
module top;
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reg [79:0] str;
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integer val;
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initial begin
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// This should be a not defined in any module message.
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$this_icarus_call_should_not_exist;
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str = "5";
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// This should be a system function is being called as a task error.
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$sscanf(str, "%d", val);
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// This should be a system task is being called as a function error.
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val = $display;
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end
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endmodule
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