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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
24 lines
483 B
Verilog
24 lines
483 B
Verilog
// This tests that the individual bits of a uwire are checked for
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// double-driving individually. The code below uses a packed struct
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// to represent individual bits.
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module test;
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struct packed {
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logic [15:0] hig;
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logic [15:0] low;
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} foo;
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assign foo.low = 'haaaa;
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assign foo.hig = 'h5555;
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initial begin
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#1 if (foo !== 'h5555aaaa) begin
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$display("FAILED -- foo=%h", foo);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // test
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