mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
10 lines
320 B
Verilog
10 lines
320 B
Verilog
module top;
|
|
// This should be okay (the trimmed bits match the enum MSB).
|
|
enum reg[3:0] {VAL1, XX1='bxxxxx} en1;
|
|
// But these should fail because the trimmed bits do not match the enum MSB.
|
|
enum reg[3:0] {VAL2, XX2='b0xxxx} en2;
|
|
enum reg[3:0] {VAL3, XX3='b0xxxxx} en3;
|
|
|
|
initial $display("FAILED");
|
|
endmodule
|