83 lines
1.8 KiB
ReStructuredText
83 lines
1.8 KiB
ReStructuredText
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The VHDL Code Generator (-tvhdl)
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================================
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Icarus Verilog contains a code generator to emit VHDL from the Verilog
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netlist. This allows Icarus Verilog to function as a Verilog to VHDL
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translator.
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Invocation
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----------
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To translate a Verilog program to VHDL, invoke "iverilog" with the -tvhdl
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flag::
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% iverilog -t vhdl -o my_design.vhd my_design.v
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The generated VHDL will be placed in a single file (a.out by default), even if
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the Verilog is spread over multiple files.
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Flags
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-----
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* -pdebug=1
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Print progress messages as the code generator visits each part of the
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design.
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* -pdepth=N
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Only output VHDL entities for modules found at depth < N in the
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hierarchy. N=0, the default, outputs all entities. For example, -pdepth=1
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outputs only the top-level entity.
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Supported Constructs
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--------------------
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TODO
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Limitations
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-----------
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Signal Values and Resolution
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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There are several cases where the behaviour of the translated VHDL deviates
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from the source Verilog:
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* The result of division by zero is x in Verilog but raises an exception in
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VHDL.
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* Similarly, the result of reading past the end of an array in Verilog is x,
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whereas VHDL raises an exception.
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* Any signal that is driven by two or more processes will have the value
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'U'. This is the result of the signal resolution function in the
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std_logic_1164 package.
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Constructs Not Supported
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^^^^^^^^^^^^^^^^^^^^^^^^
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The following Verilog constructs cannot be translated to VHDL:
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* fork and join
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* force and release
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* disable
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* real-valued variables
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* switches
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* hierarchical dereferencing
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Other Limitations
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^^^^^^^^^^^^^^^^^
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* The test expressions in case statements must be constant.
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* Translation of a parameter to a corresponding VHDL generic
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declaration. Instead the default parameter value is used.
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