62 lines
1.8 KiB
ReStructuredText
62 lines
1.8 KiB
ReStructuredText
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The PCB Code Generator (-tpcb)
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==============================
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The PCB target code generator is designed to allow a user to enter a netlist
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in Verilog format, then generate input files for the GNU PCB layout program.
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Invocation
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----------
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The PCB target code generation is invoked with the -tpcb flag to the iverilog
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command. The default output file, "a.out", contains the generated .PCB
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file. Use the "-o" flag to set the output file name explicitly. The default
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output file contains only the elements. To generate a "netlist" file, add the
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flag "-pnetlist=<path>" command line flag.
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Altogether, this example generates the foo.net and foo.pcb files from the
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foo.v source file::
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% iverilog -tpcb -ofoo.pcb -pnetlist=foo.net foo.v
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Flags
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-----
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* -o <path>
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Set the output (pcb) file path
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* -pnetlist=path
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Write a netlist file to the given path.
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Attributes Summary
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------------------
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Attributes are attached to various constructs using the Verilog "(\* \*)"
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attribute syntax.
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* ivl_black_box
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Attached to a module declaration or module instantiation, this indicates
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that the module is a black box. The code generator will create an element
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for black box instances.
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Parameters Summary
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------------------
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Within modules, The PCB code generator uses certain parameters to control
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details. Parameters may have defaults, and can be overridden using the usual
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Verilog parameter override syntax. Parameters have preferred types.
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* description (string, default="")
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The "description" is a text string that describes the black box. This string
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is written into the description field of the PCB Element.
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* value (string, default="")
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The "value" is a text tring that describes some value for the black
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box. Like the description, the code generator does not interpret this value,
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other then to write it to the appropriate field in the PCB Element."
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