iverilog/ivtest/gold/pr2859628.vcd.gold

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$date
Sun May 15 18:19:07 2022
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module top $end
$upscope $end
$scope module top $end
$var reg 4 ! \array[0] [3:0] $end
$upscope $end
$scope module top $end
$var reg 4 " \array[1] [3:0] $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
bx "
bx !
$end
#1