146 lines
3.6 KiB
C
146 lines
3.6 KiB
C
/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: fpga.c,v 1.5 2001/09/16 01:48:16 steve Exp $"
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#endif
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# include "config.h"
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/*
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* This is a null target module. It does nothing.
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*/
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# include <ivl_target.h>
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# include "fpga_priv.h"
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/* This is the opened xnf file descriptor. It is the output that this
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code generator writes to. */
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FILE*xnf = 0;
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const char*part = 0;
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const char*arch = 0;
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device_t device = 0;
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static int show_process(ivl_process_t net, void*x)
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{
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fprintf(stderr, "fpga target: unsynthesized behavioral code\n");
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return 0;
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}
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static void show_pads(ivl_scope_t scope)
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{
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unsigned idx;
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if (device->show_pad == 0)
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return;
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for (idx = 0 ; idx < ivl_scope_sigs(scope) ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(scope, idx);
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const char*pad;
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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pad = ivl_signal_attr(sig, "PAD");
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if (pad == 0)
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continue;
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device->show_pad(sig, pad);
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}
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}
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/*
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* This is the main entry point that ivl uses to invoke me, the code
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* generator.
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*/
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int target_design(ivl_design_t des)
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{
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ivl_scope_t root = ivl_design_root(des);
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const char*path = ivl_design_flag(des, "-o");
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xnf = fopen(path, "w");
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if (xnf == 0) {
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perror(path);
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return -1;
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}
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part = ivl_design_flag(des, "part");
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if (part && (part[0] == 0))
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part = 0;
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arch = ivl_design_flag(des, "arch");
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if (arch && (arch[0] == 0))
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arch = 0;
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if (arch == 0)
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arch = "generic-xnf";
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device = device_from_arch(arch);
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if (device == 0) {
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fprintf(stderr, "Unknown architecture arch=%s\n", arch);
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return -1;
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}
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/* Call the device driver to generate the netlist header. */
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device->show_header(des);
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/* Catch any behavioral code that is left, and write warnings
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that it is not supported. */
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ivl_design_process(des, show_process, 0);
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/* Get the pads from the design, and draw them to connect to
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the associated signals. */
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show_pads(root);
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/* Scan the scopes, looking for gates to draw into the output
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netlist. */
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show_scope_gates(root, 0);
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/* Call the device driver to close out the file. */
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device->show_footer(des);
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fclose(xnf);
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xnf = 0;
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return 0;
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}
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/*
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* $Log: fpga.c,v $
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* Revision 1.5 2001/09/16 01:48:16 steve
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* Suppor the PAD attribute on signals.
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*
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* Revision 1.4 2001/09/02 21:33:07 steve
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* Rearrange the XNF code generator to be generic-xnf
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* so that non-XNF code generation is also possible.
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*
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* Start into the virtex EDIF output driver.
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*
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* Revision 1.3 2001/09/01 02:01:30 steve
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* identity compare, and PWR records for constants.
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*
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* Revision 1.2 2001/08/31 02:59:06 steve
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* Add root port SIG records.
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*
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* Revision 1.1 2001/08/28 04:14:20 steve
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* Add the fpga target.
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*
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*/
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