32 lines
1.1 KiB
Verilog
32 lines
1.1 KiB
Verilog
module top;
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integer ival;
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real rval;
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initial begin
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$display("--- Printing as real ---");
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$display("1/0 is %f. (Should be 0 -- x prints as 0)", 1/0);
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$display("1/0.0 is %f. (Should be inf)", 1/0.0);
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$display("1.0/0 is %f. (Should be inf)", 1.0/0);
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$display("1.0/0.0 is %f. (should be inf)", 1.0/0.0);
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// Moving these two lines before the previous four lines makes 1/0 print
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// a large number, but not inf!
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rval = 0.0;
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ival = 0;
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$display("1/integer zero is %f. (Should be 0 -- x prints as 0)", 1/ival);
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$display("1/real zero is %f. (should be inf)", 1/rval);
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$display("1.0/integer zero is %f. (Should be inf)", 1.0/ival);
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$display("1.0/real zero is %f.", 1.0/rval);
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$display("\n--- Printing as integer ---");
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$display("1/0 is %d (Should be x)", 1/0);
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$display("1/0.0 is %d", 1/0.0);
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$display("1.0/0 is %d", 1.0/0);
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$display("1.0/0.0 is %d", 1.0/0.0);
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$display("1/integer zero is %d. (Should be x)", 1/ival);
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$display("1/real zero is %d.", 1/rval);
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$display("1.0/integer zero is %d.", 1.0/ival);
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$display("1.0/real zero is %d.", 1.0/rval);
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end
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endmodule
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