29 lines
296 B
Verilog
29 lines
296 B
Verilog
`timescale 1ns/10ps
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module test();
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reg ck;
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integer cnt;
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real tval;
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initial begin
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ck <= 0;
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cnt <= 0;
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tval <= 0.0;
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end
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always #2 ck <= !ck;
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always @(posedge ck) begin
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cnt <= cnt + 1;
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tval <= $realtime;
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$display ("tval = %g", tval);
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if (cnt >= 5) begin
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$finish(0);
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end
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end
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endmodule // test
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