74 lines
1.8 KiB
Verilog
74 lines
1.8 KiB
Verilog
module top;
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reg passed;
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wire wconst, wfconst, wfconstarg;
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wire wdconst = 1'b0;
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wire wdfconst = cfunc();
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wire wdfconstarg = func(1'b0);
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real rfconst;
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function automatic reg cfunc();
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cfunc = 1'b0;
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endfunction
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function automatic reg func(input reg val);
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func = val;
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endfunction
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function automatic real crfunc();
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crfunc = 2.0;
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endfunction
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assign wconst = 1'b1;
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assign wfconst = cfunc();
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assign wfconstarg = func(1'b1);
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assign rfconst = crfunc();
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initial begin
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passed = 1'b1;
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#1;
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if (wconst !== 1'b1) begin
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$display("Expected wire constant value to be 1'b1, actual is %b", wconst);
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passed = 1'b0;
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end
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if (wdconst !== 1'b0) begin
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$display("Expected wire decl constant value to be 1'b0, actual is %b", wdconst);
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passed = 1'b0;
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end
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if (wfconst !== 1'b0) begin
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$display("Expected wire constant function value to be 1'b0, actual is %b", wfconst);
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passed = 1'b0;
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end
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if (wdfconst !== 1'b0) begin
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$display("Expected wire decl constant function value to be 1'b0, actual is %b", wdfconst);
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passed = 1'b0;
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end
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if (rfconst != 2.0) begin
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$display("Expected real constant function value to be 2.0, actual is %f", rfconst);
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passed = 1'b0;
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end
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if (wfconstarg !== 1'b1) begin
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$display("Expected wire constant arg function value to be 1'b1, actual is %b", wfconstarg);
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passed = 1'b0;
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end
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if (wdfconstarg !== 1'b0) begin
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$display("Expected wire decl constant arg function value to be 1'b0, actual is %b", wdfconstarg);
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passed = 1'b0;
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end
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if (cfunc() !== 1'b0) begin
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$display("Expected constant function value to be 1'b0, actual is %b", cfunc());
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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