32 lines
472 B
Verilog
32 lines
472 B
Verilog
`celldefine
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module XOR20 (input A, input B, output Q);
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xor (Q,B,A);
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specify
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(A => Q) = (1,1);
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(B => Q) = (1,1);
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endspecify
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endmodule
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`endcelldefine
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module tb;
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reg a, b;
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wire q;
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XOR20 dut(.A(a), .B(b), .Q(q));
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initial begin
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$monitor($time,, "A=%b, B=%b, Q=%b", a, b, q);
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$sdf_annotate("ivltests/br_gh889.sdf");
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#10 ;
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a = 1;
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b = 1;
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#10 ;
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b = 0;
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#10 $finish(0);
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end
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endmodule // tb
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