53 lines
1.6 KiB
Verilog
53 lines
1.6 KiB
Verilog
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// br_gh800 (github Issue #800)
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module AssignLiterals;
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initial begin
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string s;
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// Note that the \0 in this string literal assigned to the string
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// must disappear, leaving "AB" what is actually assigned to the
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// string. See IEEE Std 1800-2017: 6.16 String data type.
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s = "A\0B";
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$display("1. '%s' len=%1d hex=%02h%02h%02h",s,s.len(), s[0], s[1], s[2]);
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if (s.len() != 2 || s != "AB" || s[0] !== 'h41 || s[1] !== 'h42) begin
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$display("FAILED");
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$finish;
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end
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s = "A\015\12B";
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$display("2. len=%1d hex=%02h%02h%02h%02h",s.len(), s[0], s[1], s[2], s[3]);
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if (s.len() != 4 || s[0] !== 'h41 || s[1] !== 'h0d
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|| s[2] !== 'h0a || s[3] !== 'h42) begin
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$display("FAILED");
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$finish;
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end
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s = {"A","\015","\012","B"};
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$display("3. len=%1d hex=%02h%02h%02h%02h",s.len(), s[0], s[1], s[2], s[3]);
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if (s.len() != 4 || s[0] !== 'h41 || s[1] !== 'h0d
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|| s[2] !== 'h0a || s[3] !== 'h42) begin
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$display("FAILED");
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$finish;
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end
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s = "A\170\171B";
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$display("4. '%s' len=%1d hex=%02h%02h%02h%02h",s,s.len(),
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s[0], s[1], s[2], s[3]);
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if (s.len() != 4 || s[0] !== 'h41 || s[1] !== 'h78 || s[2] !== 'h79
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|| s[3] !== 'h42) begin
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$display("FAILED");
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$finish;
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end
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s = {"A",8'o15,8'o12,"\012","B"};
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$display("5. len=%1d hex=%02h%02h%02h%02h%02h",s.len(), s[0], s[1], s[2], s[3], s[4]);
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if (s.len() != 5 || s[0] !== 'h41 || s[1] !== 'h0d
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|| s[2] !== 'h0a || s[3] !== 'h0a || s[4] !== 'h42) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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