32 lines
565 B
Verilog
32 lines
565 B
Verilog
module top;
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parameter pval = 7;
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string sval, strv, strc;
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real ridx;
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integer in;
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reg cav, cac;
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reg vv, vc, pv, pc, sv, sc;
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integer calv, calc;
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integer vlv, vlc;
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assign cav = in[ridx];
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assign cac = in[0.5];
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assign calv[ridx] = 1'b1;
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assign calc[0.5] = 1'b1;
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initial begin
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in = 7;
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sval = "ABC";
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ridx = 0.5;
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vv = in[ridx];
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vc = in[0.5];
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vlv[ridx] = 1'b1;
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vlc[0.5] = 1'b1;
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pv = pval[ridx];
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pc = pval[0.5];
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sv = sval[ridx];
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sc = sval[0.5];
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strv[ridx] = "a";
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strc[0.5] = "a";
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end
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endmodule
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