202 lines
8.8 KiB
HTML
202 lines
8.8 KiB
HTML
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<title>The Verilog ‘95 Code Generator (-tvlog95) — Icarus Verilog documentation</title>
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<section id="the-verilog-95-code-generator-tvlog95">
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<h1>The Verilog ‘95 Code Generator (-tvlog95)<a class="headerlink" href="#the-verilog-95-code-generator-tvlog95" title="Link to this heading">¶</a></h1>
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<p>Icarus Verilog contains a code generator to emit 1995 compliant Verilog from
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the input Verilog netlist. This allows Icarus Verilog to function as a Verilog
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> 1995 to Verilog 1995 translator. The main goal of the project was to convert
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@*, ANSI style arguments and other constructs to something allowed in 1995
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Verilog.</p>
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<section id="invocation">
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<h2>Invocation<a class="headerlink" href="#invocation" title="Link to this heading">¶</a></h2>
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<p>To translate a Verilog program to 1995 compliant Verilog, invoke “iverilog”
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with the -tvlog95 flag:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -tvlog95 -o my_design_95.v my_design.v
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</pre></div>
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</div>
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<p>The generated Verilog will be placed in a single file (a.out by default), even
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if the input Verilog is spread over multiple files.</p>
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</section>
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<section id="generator-flags">
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<h2>Generator Flags<a class="headerlink" href="#generator-flags" title="Link to this heading">¶</a></h2>
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<ul>
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<li><p>-pspacing=N</p>
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<p>Set the indent spacing (the default is 2).</p>
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</li>
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<li><p>-pallowsigned=1</p>
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<p>Allow emitting the various signed constructs as an extension to 1995 Verilog
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(off by default).</p>
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</li>
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<li><p>-pfileline=1</p>
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<p>Emit the original file and line information as a comment for each generated
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line (off by default).</p>
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</li>
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</ul>
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</section>
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<section id="structures-that-cannot-be-converted-to-1995-compatible-verilog">
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<h2>Structures that cannot be converted to 1995 compatible Verilog<a class="headerlink" href="#structures-that-cannot-be-converted-to-1995-compatible-verilog" title="Link to this heading">¶</a></h2>
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<p>The following Verilog constructs are not translatable to 1995 compatible Verilog:</p>
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<ul class="simple">
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<li><p>Automatic tasks or functions.</p></li>
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<li><p>The power operator (**). Expressions of the form (2**N)**<variable> (where N
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is a constant) can be converter to a shift.</p></li>
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<li><p>Some System Verilog constructs (e.g. final blocks, ++/– operators,
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etc.). 2-state variables are converted to 4-state variables.</p></li>
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</ul>
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<p>Icarus extensions that cannot be translated:</p>
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<ul class="simple">
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<li><p>Integer constants greater than 32 bits.</p></li>
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<li><p>Real valued nets.</p></li>
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<li><p>Real modulus.</p></li>
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<li><p>Most Verilog-A constructs.</p></li>
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</ul>
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</section>
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<section id="known-issues-and-limitations">
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<h2>Known Issues and Limitations<a class="headerlink" href="#known-issues-and-limitations" title="Link to this heading">¶</a></h2>
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<p>Some things are just not finished and should generate an appropriate
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warning. Here is a list of the major things that still need to be looked at.</p>
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<ul class="simple">
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<li><p>There are still a few module instantiation port issues (pr1723367 and
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partselsynth).</p></li>
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<li><p>inout ports are not converted (tran-VP).</p></li>
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<li><p>Variable selects of a non-zero based vector in a continuous assignment are
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not converted.</p></li>
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<li><p>There is no support for translating a zero repeat in a continuous
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assignment. It is currently just dropped.</p></li>
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<li><p>A pull device connected to a signal select is not translated correctly (this
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may be fixed).</p></li>
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<li><p>L-value indexed part selects with a constant undefined base in a continuous
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assignment are not translated.</p></li>
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<li><p>Logic gates are not arrayed exactly the same as the input and the instance
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name is not always the same.</p></li>
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<li><p>The signed support does not generate $signed() or $unsigned() function calls
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in a continuous assignment expression.</p></li>
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<li><p>The special power operator cases are not converted in a continuous
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assignment.</p></li>
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<li><p>Currently a signed constant that sets the MSB in an unsigned context will be
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displayed as a negative value (e.g. bit = 1 translates to bit = -1).</p></li>
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<li><p>Can net arrays, etc. be unrolled?</p></li>
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<li><p>Can generate blocks be converted?</p></li>
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</ul>
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</section>
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</section>
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</div>
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<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
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<div class="sphinxsidebarwrapper">
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<h1 class="logo"><a href="../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">The Icarus Verilog Targets</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-stub.html">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-null.html">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-sizer.html">The sizer Code Analyzer (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-blif.html">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../developer/index.html">Icarus Verilog Developer Support</a></li>
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</ul>
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<div class="relations">
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<h3>Related Topics</h3>
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<ul>
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<li><a href="../index.html">Documentation overview</a><ul>
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<li><a href="index.html">The Icarus Verilog Targets</a><ul>
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<li>Previous: <a href="tgt-vhdl.html" title="previous chapter">The VHDL Code Generator (-tvhdl)</a></li>
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<li>Next: <a href="tgt-pcb.html" title="next chapter">The PCB Code Generator (-tpcb)</a></li>
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