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167 lines
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<title>The sizer Code Analyzer (-tvvp) — Icarus Verilog documentation</title>
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<section id="the-sizer-code-analyzer-tvvp">
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<h1>The sizer Code Analyzer (-tvvp)<a class="headerlink" href="#the-sizer-code-analyzer-tvvp" title="Link to this heading">¶</a></h1>
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<p>The sizer target does not generate any code. Instead it will print statistics about the Verilog code.</p>
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<p>It is important to synthesize the Verilog code before invoking the sizer. This can be done with the <cite>-S</cite> flag passed to iverilog. Note, that behavioral code can not be synthesized and will generate a warning when passed to the sizer.</p>
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<p>Example command:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -o sizer.txt -tsizer -S -s top input.v
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</pre></div>
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</div>
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<p>With this example code:</p>
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<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="k">module</span><span class="w"> </span><span class="n">top</span><span class="w"> </span><span class="p">(</span>
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<span class="w"> </span><span class="k">input</span><span class="w"> </span><span class="n">clock</span><span class="p">,</span>
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<span class="w"> </span><span class="k">input</span><span class="w"> </span><span class="n">reset</span><span class="p">,</span>
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<span class="w"> </span><span class="k">output</span><span class="w"> </span><span class="n">blink</span>
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<span class="p">);</span>
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<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="n">out</span><span class="p">;</span>
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<span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">@(</span><span class="k">posedge</span><span class="w"> </span><span class="n">clock</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span>
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<span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">reset</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span>
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<span class="w"> </span><span class="n">out</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="mb">'b0</span><span class="p">;</span>
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<span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="k">else</span><span class="w"> </span><span class="k">begin</span>
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<span class="w"> </span><span class="n">out</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="o">!</span><span class="n">out</span><span class="p">;</span>
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<span class="w"> </span><span class="k">end</span>
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<span class="w"> </span><span class="k">end</span>
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<span class="w"> </span><span class="k">assign</span><span class="w"> </span><span class="n">blink</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">out</span><span class="p">;</span>
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<span class="k">endmodule</span>
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</pre></div>
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</div>
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<p>The resulting <cite>sizer.txt</cite> will contain:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>**** module/scope: top
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Flip-Flops : 1
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Logic Gates : 3
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MUX[2]: 1 slices
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LOG[13]: 1 unaccounted
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LOG[14]: 1 unaccounted
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**** TOTALS
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Flip-Flops : 1
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Logic Gates : 3
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MUX[2]: 1 slices
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LOG[13]: 1 unaccounted
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LOG[14]: 1 unaccounted
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</pre></div>
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</div>
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</section>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">The Icarus Verilog Targets</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-stub.html">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-null.html">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vlog95.html">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">The sizer Code Analyzer (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-blif.html">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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<li>Previous: <a href="tgt-pal.html" title="previous chapter">The PAL Code Generator (-tpal)</a></li>
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