180 lines
7.4 KiB
HTML
180 lines
7.4 KiB
HTML
<!DOCTYPE html>
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<html lang="en" data-content_root="../">
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<meta charset="utf-8" />
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<meta name="viewport" content="width=device-width, initial-scale=1.0" /><meta name="viewport" content="width=device-width, initial-scale=1" />
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<title>The PCB Code Generator (-tpcb) — Icarus Verilog documentation</title>
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<link rel="next" title="The FPGA Code Generator (-tfpga)" href="tgt-fpga.html" />
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</head><body>
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<div class="document">
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<div class="bodywrapper">
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<div class="body" role="main">
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<section id="the-pcb-code-generator-tpcb">
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<h1>The PCB Code Generator (-tpcb)<a class="headerlink" href="#the-pcb-code-generator-tpcb" title="Link to this heading">¶</a></h1>
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<p>The PCB target code generator is designed to allow a user to enter a netlist
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in Verilog format, then generate input files for the GNU PCB layout program.</p>
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<section id="invocation">
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<h2>Invocation<a class="headerlink" href="#invocation" title="Link to this heading">¶</a></h2>
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<p>The PCB target code generation is invoked with the -tpcb flag to the iverilog
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command. The default output file, “a.out”, contains the generated .PCB
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file. Use the “-o” flag to set the output file name explicitly. The default
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output file contains only the elements. To generate a “netlist” file, add the
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flag “-pnetlist=<path>” command line flag.</p>
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<p>Altogether, this example generates the foo.net and foo.pcb files from the
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foo.v source file:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -tpcb -ofoo.pcb -pnetlist=foo.net foo.v
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</pre></div>
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</div>
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</section>
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<section id="flags">
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<h2>Flags<a class="headerlink" href="#flags" title="Link to this heading">¶</a></h2>
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<ul>
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<li><p>-o <path></p>
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<p>Set the output (pcb) file path</p>
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</li>
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<li><p>-pnetlist=path</p>
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<p>Write a netlist file to the given path.</p>
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</li>
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</ul>
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</section>
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<section id="attributes-summary">
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<h2>Attributes Summary<a class="headerlink" href="#attributes-summary" title="Link to this heading">¶</a></h2>
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<p>Attributes are attached to various constructs using the Verilog “(* *)”
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attribute syntax.</p>
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<ul>
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<li><p>ivl_black_box</p>
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<p>Attached to a module declaration or module instantiation, this indicates
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that the module is a black box. The code generator will create an element
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for black box instances.</p>
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</li>
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</ul>
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</section>
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<section id="parameters-summary">
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<h2>Parameters Summary<a class="headerlink" href="#parameters-summary" title="Link to this heading">¶</a></h2>
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<p>Within modules, The PCB code generator uses certain parameters to control
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details. Parameters may have defaults, and can be overridden using the usual
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Verilog parameter override syntax. Parameters have preferred types.</p>
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<ul>
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<li><p>description (string, default=””)</p>
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<p>The “description” is a text string that describes the black box. This string
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is written into the description field of the PCB Element.</p>
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</li>
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<li><p>value (string, default=””)</p>
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<p>The “value” is a text tring that describes some value for the black
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box. Like the description, the code generator does not interpret this value,
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other then to write it to the appropriate field in the PCB Element.”</p>
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</li>
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</ul>
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</section>
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</section>
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</div>
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</div>
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</div>
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<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
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<div class="sphinxsidebarwrapper">
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<h1 class="logo"><a href="../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">The Icarus Verilog Targets</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-stub.html">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-null.html">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vlog95.html">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-sizer.html">The sizer Code Analyzer (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-blif.html">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../developer/index.html">Icarus Verilog Developer Support</a></li>
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</ul>
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<div class="relations">
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<h3>Related Topics</h3>
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<ul>
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<li><a href="../index.html">Documentation overview</a><ul>
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<li><a href="index.html">The Icarus Verilog Targets</a><ul>
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<li>Previous: <a href="tgt-vlog95.html" title="previous chapter">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li>Next: <a href="tgt-fpga.html" title="next chapter">The FPGA Code Generator (-tfpga)</a></li>
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</ul></li>
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</ul></li>
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</ul>
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</div>
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</div>
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©2024-2025, Stephen Williams.
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<a href="../_sources/targets/tgt-pcb.rst.txt"
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