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<section id="the-pal-code-generator-tpal">
<h1>The PAL Code Generator (-tpal)<a class="headerlink" href="#the-pal-code-generator-tpal" title="Link to this heading"></a></h1>
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<p class="admonition-title">Warning</p>
<p>This code generator is currently not included in Icarus Verilog.</p>
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<p>The PAL target generates JEDEC output for a Programmable Array Logic.</p>
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
<li class="toctree-l1 current"><a class="reference internal" href="index.html">The Icarus Verilog Targets</a><ul class="current">
<li class="toctree-l2"><a class="reference internal" href="tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
<li class="toctree-l2"><a class="reference internal" href="tgt-stub.html">The stub Code Generator (-tstub)</a></li>
<li class="toctree-l2"><a class="reference internal" href="tgt-null.html">The null Code Generator (-tnull)</a></li>
<li class="toctree-l2"><a class="reference internal" href="tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
<li class="toctree-l2"><a class="reference internal" href="tgt-vlog95.html">The Verilog 95 Code Generator (-tvlog95)</a></li>
<li class="toctree-l2"><a class="reference internal" href="tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
<li class="toctree-l2"><a class="reference internal" href="tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
<li class="toctree-l2 current"><a class="current reference internal" href="#">The PAL Code Generator (-tpal)</a></li>
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