127 lines
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HTML
127 lines
5.0 KiB
HTML
<!DOCTYPE html>
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<title>The null Code Generator (-tnull) — Icarus Verilog documentation</title>
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<link rel="next" title="The VHDL Code Generator (-tvhdl)" href="tgt-vhdl.html" />
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<link rel="prev" title="The stub Code Generator (-tstub)" href="tgt-stub.html" />
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<div class="document">
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<section id="the-null-code-generator-tnull">
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<h1>The null Code Generator (-tnull)<a class="headerlink" href="#the-null-code-generator-tnull" title="Link to this heading">¶</a></h1>
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<p>The null target generates no code. Invoking this code generator causes no code
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generation to happen.</p>
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</section>
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</div>
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</div>
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<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
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<div class="sphinxsidebarwrapper">
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<h1 class="logo"><a href="../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">The Icarus Verilog Targets</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-stub.html">The stub Code Generator (-tstub)</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">The null Code Generator (-tnull)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vhdl.html">The VHDL Code Generator (-tvhdl)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-vlog95.html">The Verilog ‘95 Code Generator (-tvlog95)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pcb.html">The PCB Code Generator (-tpcb)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-fpga.html">The FPGA Code Generator (-tfpga)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-sizer.html">The sizer Code Analyzer (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="tgt-blif.html">The BLIF Code Generator (-tblif)</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../developer/index.html">Icarus Verilog Developer Support</a></li>
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</ul>
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<div class="relations">
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<h3>Related Topics</h3>
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<ul>
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<li><a href="../index.html">Documentation overview</a><ul>
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<li><a href="index.html">The Icarus Verilog Targets</a><ul>
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<li>Previous: <a href="tgt-stub.html" title="previous chapter">The stub Code Generator (-tstub)</a></li>
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<li>Next: <a href="tgt-vhdl.html" title="next chapter">The VHDL Code Generator (-tvhdl)</a></li>
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</ul></li>
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</ul></li>
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©2024-2025, Stephen Williams.
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<a href="../_sources/targets/tgt-null.rst.txt"
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