32 lines
679 B
Verilog
32 lines
679 B
Verilog
// When registering a simulation time callback, some simulators interpret
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// the specified time value as relative to the current simulation time. To
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// support this case, define the macro CB_TIME_IS_RELATIVE when compiling
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// this module.
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module main;
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integer val;
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initial begin
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val = 0;
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#1 $poke_at_simtime(val, 1, 10);
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`ifdef CB_TIME_IS_RELATIVE
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#1;
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`endif
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#8 if (val !== 0) begin
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$display("FAILED -- val==%0d before delayed poke", val);
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$finish;
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end
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#1 if (val !== 1) begin
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$display("FAILED -- val==%0d: poke didn't happen", val);
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$finish;
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end
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$display("PASSED");
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$finish(0);
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end
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endmodule // main
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