70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
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// Michael Runyan (mrunyan at chiaro.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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module test;
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reg [5:0] addr;
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reg [75:0] m_poke[4:0];
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reg [75:0] m_peek[4:0];
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task f_copy_for_buggy_eda_vendor;
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integer i;
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reg [75:0] tmp;
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begin
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for (i = 0; i < 5; i = i + 1) begin
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tmp = m_poke[i];
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m_peek[i] = tmp;
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end
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end
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endtask
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task f_copy;
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integer i;
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begin
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for (i = 0; i < 5; i = i + 1) begin
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m_peek[i] = m_poke[i];
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end
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end
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endtask
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task f_dump;
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integer i;
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begin
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for (i = 0; i < 5; i = i + 1) begin
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$display ("%0d: m_poke <=> m_peek, 0x%x <=> 0x%x%s",
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i, m_poke[i], m_peek[i],
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m_poke[i] !== m_peek[i] ? " - ERROR" : "");
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end
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end
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endtask
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initial begin
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#0;
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$mempoke;
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#10;
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f_copy;
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//f_copy_buggy_eda_vendor;
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#10;
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$mempeek;
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#10;
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f_dump;
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end
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endmodule
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