18 lines
533 B
Verilog
18 lines
533 B
Verilog
//---------------------------------------------------------------------------
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//
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//---------------------------------------------------------------------------
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module xor_try;
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reg [1:0] inp_xor; // The two-bit inputs to the XOR
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reg out_xor; // The XOR output
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reg clk;
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initial begin clk = 1'b1; $sn; #160 $finish(0); end
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always #50 clk = ~clk;
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// The clock
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always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]);
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// The actual operation
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endmodule
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