16 lines
348 B
Verilog
16 lines
348 B
Verilog
module test;
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reg [15:0] r;
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integer i, i2;
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real r1, r2;
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initial begin
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i = $mytest(r, i2, r1, r2);
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if (i !== 69 || r !== 11 || i2 !== 22 || r1 != 3.3 || r2 != 4.4) begin
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$display("i = %0d, r = %0d, i2 = %0d, r1 = %f, r2 = %f",
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i, r, i2, r1, r2);
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$display("FAILED");
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end else
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$display("PASSED");
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end
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endmodule
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