30 lines
481 B
Verilog
30 lines
481 B
Verilog
module top;
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reg [7:0] a;
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reg [7:0] b;
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reg [7:0] c;
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integer retcode;
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initial
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begin
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#0; // avoid T0 race
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a = 0;
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b = 0;
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c = 0;
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/* Use VPI to set values on these registers */
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retcode = $example(a, b, c);
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end
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always @(a)
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$display("%t The value of A is: %b", $time, a);
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always @(b)
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$display("%t The value of B is: %b", $time, b);
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always @(c)
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$display("%t The value of C is: %b", $time, c);
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endmodule // top
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